Yep, I know you guys were too smart to take things at face value :thumb: The circuit on the left looks superficially "better" because of its lower parts count and marginally higher gain, but the circuit on the right does indeed give more predictable performance over the Vgs spread that can be expected with a JFET.
By the way, these circuits were actually built, not simulated.
Buttachunk: Unless I'm really missing something, I don't see the point of increasing Vgg and putting a cap across R5. Increasing Vgg means a higher Vs and therefore a further reduction of Vds (and maximum output swing). And R1+(R4||R5) appear in shunt with the input signal, not in series, so I don't see any benefit in AC bypassing of (R4||R5).
(Vgs= gate-source voltage, Vgg= gate voltage relative to ground, Vs= source voltage relative to ground, Vds= drain-source voltage).