JFET + cascode inside feedback loop - stable?

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steveh

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Joined
Nov 18, 2010
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In the attachment, I've shown an outline circuit (biasing absent) in which the global feedback loop is made stable by C2.  C2 then forms a feedback loop around the two JFETs.  For the two JFETs, I was thinking of using the same type, with the higher Idss/Vcutoff one as the cascode.

With two very similar parts operating at the same current, would this arrangement be stable?  If not, what could be done to stabilise this inner loop?  Or, if two different JFET types were used, what properties should the cascode FET have relative to the common-source FET (what to look for in datasheets)?

Thanks,
Stephen

 

Attachments

  • JFET_cascode.gif
    JFET_cascode.gif
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Hi,
In a cascode design the cascoding transistor (the upper one) should have his grid/base ac coupled to ground.
I think a bipolar transistor is better as a cascoding device.
Cheers
Nkt
 
Haven't I seen this Q on some other forum too? 8)

Usually this cascode arrangement should be stable without any further means. If practical investigations show otherwise, minimizing layout parasitics is the first thing to do, perhaps followed by a gate resistor for the cascode.

In a cascode design the cascoding transistor (the upper one) should have his grid/base ac coupled to ground.

The shown arrangement is actually superior to the standard cascode approach, as it provides much higher output impedance and keeps the Vds of the input transistor essentially independent from input voltage swing (i.e. reduces common-mode distortion).

Samuel
 
Samuel Groner said:
The shown arrangement is actually superior to the standard cascode approach, as it provides much higher output impedance and keeps the Vds of the input transistor essentially independent from input voltage swing (i.e. reduces common-mode distortion).

Higher output impedance ?? Could you be more precise about that ??
 
Samuel Groner said:
Haven't I seen this Q on some other forum too? 8)

Only if you were quick. It fell off the front page after about an hour.

Usually this cascode arrangement should be stable without any further means. If practical investigations show otherwise, minimizing layout parasitics is the first thing to do, perhaps followed by a gate resistor for the cascode.

Thanks for this. If resistor is needed, how is it sized? As a low pass with the jfet's capacitance?

 
What is the circuit for?  Why are you cascoding?  Cascodes are usually for ..
  • reduced Miller capacitance for better HF.  But your C2 puts in even more Miller capacitance so the HF is even poorer.
  • high output Z.  But U1 makes this low.
 
If resistor is needed, how is it sized? As a low pass with the jfet's capacitance?

Usually "gate stopper" resistors are in the ~100 Ohm range; the exact value must often be determined experimentally. Start with 100 Ohm, increase if necessary and reduce if possible. Controlling parasitic oscillation is not as conceptually pleasing as e.g. standard Miller compensation. It has more to do with parasitic circuit behaviour, which is far less easy to predict.

High output Z. But U1 makes this low.

U1 does make the output impedance of the overall amplifier low, but it surely does not reduce the impedance at the node of J2 drain! Having this node as high-impedance as possible does make sense as it will improve o/l gain at low frequencies. Not saying that the amplifier is perfect as shown, but the cascode does make some sense.

Samuel
 
Samuel Groner said:
If resistor is needed, how is it sized? As a low pass with the jfet's capacitance?

Usually "gate stopper" resistors are in the ~100 Ohm range; the exact value must often be determined experimentally. Start with 100 Ohm, increase if necessary and reduce if possible. Controlling parasitic oscillation is not as conceptually pleasing as e.g. standard Miller compensation. It has more to do with parasitic circuit behaviour, which is far less easy to predict.

Thanks for this advice, very useful.

[from Ricardo's post]
What is the circuit for?  Why are you cascoding?  Cascodes are usually for ..
- reduced Miller capacitance for better HF.  But your C2 puts in even more Miller capacitance so the HF is even poorer.
- high output Z.  But U1 makes this low.

The circuit started out as my learning about JFETs, but I may build it for headphones as my player doesn't go loud enough on its own for some songs.

For information, to expand on Samuel's posts, the whole circuit gives simulated distortion of (at 10Vp-p output):
a) 0.003% THD as shown in the first post.
b) 0.003% THD with C2 removed.
c) 0.098% THD with C2 removed and the cascode J2 removed.
d) 0.010% THD with 10pF for C2 and J2 gate referred to ground (via ideal DC voltage source to keep DC conditions the same as case a)), as suggested by Niketouille.

Note that case a) has higher levels of 4th and higher harmonics than case b) (by 10-17 dB each), but second harmonic dominates by far so the overall THD is approximately the same.

Cheers,
Stephen
 
Samuel Groner said:
www.essex.ac.uk/csee/research/audio_lab/malcolmspubdocs/J10%20Enhanced%20cascode.pdf

He shows the improvement for a BJT cascode transistor, but the effect is the very same for a self-biased cascode.

Off topic by me but, yes, that's a good paper and worth the read - I also linked to it recently in another thread.  This 'enhanced' arrangement seems to now get called the "Hawksford Cascode" even though others had done it before Hawksford's publication. 


I also don't see why stability would be an issue with putting an extra cascoded stage in front as the dominant pole inside the Op-Amp will still be the same as it ever was. 
Regarding the question over upper and lower device characteristics:  Generally the upper device has sufficient Vgs and is higher Idss than the lower device.  If I were doing this, it would probably mean that the two devices weren't the same type but each to his/her own  :)

 

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