Critique my first PCB design

I've been learning Eagle. As my first project I chose the monoing section from NYD's monitor controller. Since this will go in my monitor controller, it's important to design for low noise and distortion.

Notes
CA1 and CA2 are optional jumpers to bias the 5532s into class A via a 3K resistor to V-. (The +5 and -5V don't mean anything, just using them to connect nets.)

Decoupling rail-to-ground is done at C3 and C4 (0.1u NP0), using damping resistors R19 and R20, to separate dirty ground (to be connected at chassis star ground). C5 rail-to-rail is 10u electrolytic.

C1 and C2 are big polypropylene types off-board, thus C1 and C2 in and out.

L (+/-) and R are inputs, OL and OR are outputs.

Questions
1) Does my layout look ok for low noise/distortion?
2) Should I do a ground pour on the top also?

Eagle schematic

Eagle layout

Did you run DRC on that panel?

A few notes:
1) Go find a good design rules file for Eagle - I like SparkFun's one (http://www.sparkfun.com/tutorial/Eagle-DFM/SparkFun.dru).  Save the file in the Design Rule's directly, then run DRC with it once.  It will adjust the net clearances for 8mil trace and 8mil space which seems like a good starting point.
2) I'm guessing the DRC will fail:  several resistors appear to short to traces, and you'll get net clearance violations (especially around R16)
3) Make sure you have the proper layers turned on before DRC - use the command "display none 1 16 17 18 19 20 21 23 25"
4) Try to place components and route on a grid:  you can force components to the present grid by holding Ctrl-Shift when in "move" mode:  the component's centers will move to the present grid.
5) Set your grid to 50 mils, and try starting with 25mil trace width.  This means you can route two traces next to each other with 25 mils spacing.
6) I would turn on "Generate thermals for vias" (in one of the design rules panes) - this will turn on thermal reliefs for connections to the ground plane and make those components easier/better to solder

Thanks, that was really helpful. I ran DRC and fixed the clearance/shorting problems.

The only problem is that I am getting lots of Stop Mask errors on layer 29. Obviously when I display the layers you said to display, they don't show up... but should I be worried?

Dylan W said:

Decoupling rail-to-ground is done at C3 and C4 (0.1u NP0)

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0.1uF is not enough. You should add electrolytics (10-47uF)

, using damping resistors R19 and R20, to separate dirty ground (to be connected at chassis star ground).

Click to expand...

Big mistake. The caps should go to the stage's reference via the shortest, sturdiest route. This is one case where all grounds should be tied together via the ground plane.

C5 rail-to-rail is 10u electrolytic.

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The utility of a rail-to-rail decoupling cap is debatable. However, it can do no harm, so why not?

C1 and C2 are big polypropylene types off-board, thus C1 and C2 in and out.

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Why? Having these caps hanging on wires is probably more damageable than having good quality bypolar 'lytics on the board.

1) Does my layout look ok for low noise/distortion?

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I would say that the lay-out itself seems innocuous, but definitely, the jagged traces do not make for a nice looking PCB.
I can see a number of improvements to the routing that would prevent some of the convoluted traces.
Speaking of noise, the 16.2k resistors hanging on the non-inverting inputs are no good. I understand you've put them in order to eliminate DC offset, but DC offset is not an issue. Worst case it's about 20mV, and anyway the output caps completely eliminate it. OTOH, they double the source impedance for the 5532, thus increasing noise by almost 6dB. At least you should strap a capacitor across them (0.1uF minimum); I would simply omit them.

2) Should I do a ground pour on the top also?

Click to expand...

You don't need to; doing it would not change the performance significantly. If I wanted to manufacture hundreds of it, I would have a top ground plane because it uses less chemicals.

Dylan W said:

The only problem is that I am getting lots of Stop Mask errors on layer 29. Obviously when I display the layers you said to display, they don't show up... but should I be worried?

Click to expand...

It's no problem:  it's complaining about the distance between the stop mask and the edge of the copper.  You can safely ignore it.

I would re-route on a grid:  it makes for a cleaner layout, and makes it more obvious where alternate paths exist and how to possible shift the components around to make things cleaner.

abbey road d enfer said:

Dylan W said:

using damping resistors R19 and R20, to separate dirty ground (to be connected at chassis star ground).

Click to expand...

Big mistake. The caps should go to the stage's reference via the shortest, sturdiest route. This is one case where all grounds should be tied together via the ground plane.

Click to expand...

There's a lot of talk in this thread about keeping "dirty ground" for decoupling separate, to avoid junk in the reference ground. Do you think this is unnecessary?

FYI, there are a few other circuits in this box that will be run from the same PSU (a couple balancing stages for unbalanced inputs; may also experiment with a line driver on the output).

1) Does my layout look ok for low noise/distortion?

Click to expand...

I would say that the lay-out itself seems innocuous, but definitely, the jagged traces do not make for a nice looking PCB.
I can see a number of improvements to the routing that would prevent some of the convoluted traces.
Speaking of noise, the 16.2k resistors hanging on the non-inverting inputs are no good. I understand you've put them in order to eliminate DC offset, but DC offset is not an issue. Worst case it's about 20mV, and anyway the output caps completely eliminate it. OTOH, they double the source impedance for the 5532, thus increasing noise by almost 6dB. At least you should strap a capacitor across them (0.1uF minimum); I would simply omit them.

Click to expand...

I can't take credit for this design; it's New York Dave's circuit (see attached in first post).

Dylan W said:

abbey road d enfer said:

Dylan W said:

using damping resistors R19 and R20, to separate dirty ground (to be connected at chassis star ground).

Click to expand...

Big mistake. The caps should go to the stage's reference via the shortest, sturdiest route. This is one case where all grounds should be tied together via the ground plane.

Click to expand...

There's a lot of talk in this thread about keeping "dirty ground" for decoupling separate, to avoid junk in the reference ground.

Click to expand...

I know. Check what I wrote at the time.
http://groupdiy.com/index.php?topic=37307.msg459229#msg459229

Do you think this is unnecessary?

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This may be applicable when the impedance of the dirty ground is kept very low, which is not really the case in your application.

FYI, there are a few other circuits in this box that will be run from the same PSU

Click to expand...

More reason to make sure the 0v reference that is distributed is the cleanest possible. 

1) Does my layout look ok for low noise/distortion?

Click to expand...

I would say that the lay-out itself seems innocuous, but definitely, the jagged traces do not make for a nice looking PCB.
I can see a number of improvements to the routing that would prevent some of the convoluted traces.
Speaking of noise, the 16.2k resistors hanging on the non-inverting inputs are no good. I understand you've put them in order to eliminate DC offset, but DC offset is not an issue. Worst case it's about 20mV, and anyway the output caps completely eliminate it. OTOH, they double the source impedance for the 5532, thus increasing noise by almost 6dB. At least you should strap a capacitor across them (0.1uF minimum); I would simply omit them.

Click to expand...

I can't take credit for this design; it's New York Dave's circuit (see attached in first post).

Click to expand...

I understand that, I'm just tipping you to the fact.

Thanks, both of you.

I reworked it on a grid from scratch, adding decoupling and BP coupling, and simplifying ground scheme... I'm not sure whether this is any better, since a lot of the runs are longer.

Schematic

Dylan W said:

Thanks, both of you.

I reworked it on a grid from scratch, adding decoupling and BP coupling, and simplifying ground scheme...

Click to expand...

Much better now. Still, I notice you haven't defined net classes. It's something you do in the schemo. You define categories, ground, supplies, whatever. It's not strictly necessary in such a project, but it is when you want to optimize your design.
You can do it later, just create the net classes and use the "change" tool to redefine trace width, clearance,...

  I'm not sure whether this is any better, since a lot of the runs are longer.

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The board is so small it doesn't matter much. Anyway the externally mounted film caps will do much more harm than the trace length. Think of these film caps as big antennas carrying the output voltage.
Trace length is an issue for two reasons mainly:
- Too much resistance: that is a problem when there is significant current running. It's not the case here.
- Too much stray capacitance: That could induce HF crosstalk. The usual solutions are minimizing trace length, reducing trace width and adding electrostatic guard - that's putting "inert" traces between traces that interact each other. By inert, I mean traces that are electrically stiff enough to resist the influence of other traces and that don't radiate, typically ground and supply voltages. The copper pour does exactly that, as well as reducing the resistance of the "ground" net, which minimizes the parasitic voltages developed by any currents.
There are other aspects such as trace inductance, that you don't have to worry about, it's mostly an issue for RF and digital designers.

I don't know if there is a standard for labeling components on the pcb. I have seen boards laid out with the lowest reference designator, R1, at the top left corner, and increasing to the right in rows, all horizontal components, and then all vertical components. This makes locating a specific part on a board quicker if you don't have a fancy board file program. I have also spent a lot of time looking for a suspect part on a board with randomly labeled components.

Dylan W said:

I reworked it on a grid from scratch, adding decoupling and BP coupling, and simplifying ground scheme... I'm not sure whether this is any better, since a lot of the runs are longer.

Click to expand...

Very nice, that looks a lot cleaner!

Two additional things:

First, in addition to net classes, you can also name and label nets.  Use the "NAME" function to give a net a proper name (net names in eagle default to N$<some number>): you can provide better names like "OUTPUT" or "SUM_JUNCTION".  Once you name the net, you can add a label to the net with the "LABEL" command.  This will show the name on the schematic.  You really only need power and ground supply nodes for ... well ... power and ground supplies.  All of those other nodes you can give proper names.  It really freaked me out to see you use the +5V supply node for output connections:  generally, ERC will complain if you do things like this (e.g. assign an "output" node on a package to a supply net).

You did run ERC, right?    It catches many common things like this.

Second, you went to the trouble to define two different ground nodes: PSU decoupling earth, or "dirty" 0V, and "clean" 0V.  Then you forced them to be the same via a shorting connector, which makes them electrically the same on the layout.  Thus your ground pour surrounded and connected all of those nodes together, undoing your distinction.

Eagle has a special connector for this, which allows you to run different grounds separately by name (e.g., DGND / digital ground and AGND / analog ground), and then bring them together at a single point.  You can "NAME" pours separately to keep the pours electrically separate, and then use the connector to bridge them together at your PSU filter caps (or other appropriate place).  You can also do this:  connect the grounds with a small SMD resistor layout (like an 0805), then place a pour to bridge them together.  DRC will complain, but you can make an exemption in this case.

This is a small board, probably doesn't really matter, but if you want to learn how to fix it:  Run your "dirty" ground as a separate net, and leave the pour in place for your "clean" GND node.  Then route the "dirty" grounds in their own trace when GND enters the board from the PSU.  This minimizes the possibility of common ground impedances and leaves the "clean" grounds as clean as possible, and minimizes ground impedance for the nets where it really counts.

I made a few tweaks. Now net classes define trace width, the board is smaller, and I just drew wires instead of doing the weird thing with 5V supplies (no more ERC error, which I was ignoring).

I also tried using a separate polygon for decoupling ground, to be joined near where the ground enters from the PSU with a 1206 0-ohm resistor.

Not sure if the thicker traces will result in meaningfully greater stray capacitance.

Dylan W said:

I also tried using a separate polygon for decoupling ground, to be joined near where the ground enters from the PSU with a 1206 0-ohm resistor.

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I don't see that. Well, I see the 1206 res but both sides are already connected via the copper pour. If you want to do that kind of things, you have to give the polygon another name than GND. If implemented carelessly, this will make the copper pour an electrostatic shield only and you would not beneficiate from the reduction of resistance/inductance that copper pours can offer. In larger boards, it is important to use this benefit but it is more important to separate dirty ground(s) from the clean ones, and to respect the "ground follows signal" rule. Designing the polygon can be quite challenging sometimes.

Not sure if the thicker traces will result in meaningfully greater stray capacitance.

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It will result in greater stray capacitance, but not "meaningfully". Capacitive effects are to be avoided in long parallel signal traces, and the copper pour is an excellent guard in your case.

It's difficult to see... here's top and bottom copper only.

I used DGND for the dirty ground and named the polygon separately.

Did you use vias as mount holes?
I always use 3mm holes from the "holes" library, unless I want to ground it there.
Leo..

I'd place C8/C9 close to each other, and near the power entrance. There's no need for these caps to be very close to the IC, and placing them near each other, and a bit further from the IC, greatly reduces common-impedance coupling from the distorted currents which flow through them.

Samuel