DC blocking cap and transformer weirdness

Hey folks, at the moment I'm experimenting with some ideas for a compressor based on diode bridge topology. It works fine on breadboard but there's one thing I don't quite understand. Maybe someone here can shed some light on this...

In front of the interstage transformer (OEP A262A3E in my case) there are two DC blocking caps as seen on the schematic extract from a Neve 33609 (C1 and C2). At least I believe that's what they are: DC blocking caps, right? I measured around 5 VDC on the positive lead - as expected. But the negative side (pointing to the transformer) still has about 3 VDC on both caps, where there should be almost nothing. Simulating this part of the schematic in LTSpice shows a few millivolts behind the caps - again, as expected. I also tried different caps but they seem to be fine as it's always the same.

Why is that?

You need to measure differentially, between point E and F (not from one of these relative to ground). As there is no explicit DC path from these nodes to ground (not too good practice, actually) leakage currents and parasitic resistances will define a common-mode DC voltage. This is no problem for the transformer, but I think I'd add a 10k to ground from node E and F.

Samuel

Thanks Samuel. I was suspecting something like this. There's indeed no potential difference between E and F. Will try the resistors.

As Samuel says, the transformer does not care about "to ground" voltage; it does not know where ground is.

Differential DC would be bad.

> there should be almost nothing.

Why? How would it know you expect "nothing"?

Ideally there is NO conductance from these nodes to a "nothing voltage"; the transformer insulation is "perfect".

If we also assume perfect capacitor insulation, the voltage there is utterly un-defined.

BTW, my SPICE would blow-up, complaining that it can not compute the DC at that node. If yours doesn't, it has some hidden assumption (some minimum conductance to network zero.) It can be good to know these things.

In practice we expect the large electrolytics to leak a "lot", and the transformer to leak very little. Also consider the conductance of your DC meter. For 5V in, I would expect 4.5++V on the other side. If you get 3V, your caps are very good (or your meter is low resistance).

It's not bad practice in this case; you don't need pull down resistors. The node voltage on the transformer can't exceed the 5V you already have on the other side of the caps, so it's not an issue.

Where does INTR2-1 and INTR2-2 go? Could whatever destination leak back?

Why would you want two 680u electrolytics - a single one will keep the transformer DC-free and happy?

Jakob E.

gyraf said:

Where does INTR2-1 and INTR2-2 go? Could whatever destination leak back?

Why would you want two 680u electrolytics - a single one will keep the transformer DC-free and happy?

Click to expand...

Above picture was just an example as it's pretty similar to what I actually have on breadboard. I don't know what INTR2-1 or 2 are used for in the original. In my case I even have to use 1000uF caps because anything smaller would lead to quite a heavy bass boost with the OEP tranny I'm using. These caps and a carefully tuned Zobel network on the secondary give me a highly acceptable +/- 0.2 dB from 20 to 20.000 Hz so I won't change that.

I may be wrong but I think two caps are needed because the input to the transformer is differential. The second JFET buffer is "off-screen" in the attached snippet of the schematic (originally from Igor for a modified 2254).

I tried it with the resistors as Samuel suggested but it didn't change anything (sound-wise) except for the DC-reading.

No DC bias on the cap(s). Good Practice suggests either two regular e-caps or one bipolar e-cap.

Perhaps a 680u uni-polar cap was already in the parts bin. Or the two caps looked good on the prototype.