Selecting bias resistors for a motorola J305 in a schoeps circuit

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Jonathan_D

Member
Joined
Nov 23, 2015
Messages
11
I have decided to bias my FET using the scope method outlined by zapnspark. This isn't the first schoeps type mic I have built, usually I bias the FET by twiddling the pot up and down as I talk into the mic... not very scientific but it generally sounds fine to my amateur musician non-sound engineer ears. My test circuit is the same as his (2k2, FET drain, FET source to another 2k2 to ground. 1 meg pot connected across source resistor, wiper via a 10k resistor to gate) except I'm using a 9v battery instead of a 12v supply. Also as his oscillator has an electrolytic capacitor coupling the output I haven't used the 10n capacitor to couple the input to the test circuit. I'm using his triangle wave oscillator which gives me a 1.4khz triangle wave with about 6v peak to peak.

I am using a pocket Velleman oscilloscope.

Connecting the input to the gate of the FET and the output to the source of the FET, I have the 1meg pot wound all the way down and I wind it up. Also I try winding it from up to down.

My problem is, I seem to get clipping only on the upper limit of the triangle wave, not ever a the lower limit. So I can't seem to bring about a situation where I have above and below clipping.

If I connect the scope to the drain, I have the opposite situation, clipping only visible on the lower part of the wave.

Am I doing something wrong? Is it a function of this particular type of FET? Does it matter that I'm using 9v in my test circuit rather than 12v? Is it just my cheap oscilloscope doesn't give me good enough visibility to visualise the clipping on the other end of the wave?

Finally how much does this really matter? I am recording acoustic instruments, grand piano, cello, violin. So the SPLs are probably never over 100dB.  Also I have noticed others say that using the J305 results in less distortion but I'm not sure if they're biassing it carefully or just using a "one size fits all" fixed resistor bias network or using a listen and twiddle approach like min.
 
Sorry Jonathan, but this time i'm to sleepy to read all ;)
Anyway, why you just don't set bias with the pot inside microphone circuit?
It's much easier and you have sure is't everything as it should be!
 
FETbias.doc, in my Yahoo MicBuilders directory, explains the issues and what is happening.

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At what level are you getting the clipping?

Even recording grand piano, you will have peaks well above 120dB spl
 
This is the method how I do it: connect a generator (via a capacitor) to the gate of the FET, connect the output of the microphone to a microphone amplifier. The output of the microphone amplifier is connected to a distortion meter.
Raise the level of the generator until distortion seriously increases. (Take care not to overload the microphone amplifier!)
Then adjust the bias pot for minimal distortion at high output levels.
I can get distortion as low as 0.02% at 0 dB (775 mV) output from the microphone.
(My generator produces very low distortion!)
 
If you can measure VGS(off) and IDSS, you can get very close to an approximation of the source resistance.  You need to remember that you want equal current swing between cutoff (0mA), and IDSS (which can vary wildly from FET to FET, and there may even be several bands to select from even within a single part number), which turns out should be IDSS/2.

My favorite way:  measure IDSS, then calculate IDSS/2.  Ground the gate, connect the drain to some positive voltage: say 9V.  Then use a constant current sink and trim it to IDSS/2.  So if your FET measures IDSS of 5mA, you trim your CSS to 2.5mA, and connect it to the source terminal.  Then measure the DC voltage on the source terminal:  since the gate is grounded, it represents the VGS bias needed to flow IDSS/2.  Then the source resistance is just VGS(2.5mA)/IDSS/2.  So for an example, if it takes 0.3V to flow 2.5mA, then then source resistance would be 0.3V/2.5mA = 120 ohms.

I think another common approximation is VGS(off) / IDSS which can be pretty close.
 
Usual am setting both amplitudes exactly the same using scope. Signal by capacitor to the gate and observing amplitudes at the output.
Here are some informations and mod schematic for the chinese "schoeps" if you build or mod something similar.
http://groupdiy.com/index.php?topic=61893.20
For the schematic is important last post.
 
ln76d

The adjusted circuit in the link in you post has issues. I will post two
1uf coupling caps?  AC , trucks, trains, car, foot steps etc. noise.
Removing the series output resistance? You should think about that

You don't know where the microphone might be used.
 
Gus said:
ln76d

The adjusted circuit in the link in you post has issues. I will post two
1uf coupling caps?  AC , trucks, trains, car, foot steps etc. noise.
Removing the series output resistance? You should think about that

You don't know where the microphone might be used.

Hey Gus,

i'm not sure what you mean ;)
C1/C10 is too big in your opinion and should i not remove R11/R13?
I build that circuit at least 30 times (or more  - don't remeber) in different donor microphones.
Noone ever complain.
Am also using microphones with this circuit in really different conditions.
For C1/C10 all depends on capsule, polarisation voltage and headbasket, for some 470nF is sufficient (this is max value for sdc which am using), sometimes 680nF but mostly 1uF do the job.
If the microphone body doesn't have horrible resonances (always can be damped) i don't see how this can be problematic.
For the resistors at the output - schoeps used only inductors  - this way somehow microphone sounds better (for me) i made comparison on two matched microphones too have sure :) Both microphones both configurations.
 
I think what Gus means is that you don't want a microphone to be (almost) flat to DC.
It is no problem to roll-off the frequency response below 25 Hz (or so, or even a bit higher).
 
Ahhh, ok :D

I was thinking about DC offset :D :D :D
Yep with 1uF corner is around 2Hz if we calculate only 100-150k and 1uF.
Capsule itself has roll off.
 
Matador said:
If you can measure VGS(off) and IDSS, you can get very close to an approximation of the source resistance.  You need to remember that you want equal current swing between cutoff (0mA), and IDSS (which can vary wildly from FET to FET, and there may even be several bands to select from even within a single part number), which turns out should be IDSS/2.

My favorite way:  measure IDSS, then calculate IDSS/2.  Ground the gate, connect the drain to some positive voltage: say 9V.  Then use a constant current sink and trim it to IDSS/2.  So if your FET measures IDSS of 5mA, you trim your CSS to 2.5mA, and connect it to the source terminal.  Then measure the DC voltage on the source terminal:  since the gate is grounded, it represents the VGS bias needed to flow IDSS/2.  Then the source resistance is just VGS(2.5mA)/IDSS/2.  So for an example, if it takes 0.3V to flow 2.5mA, then then source resistance would be 0.3V/2.5mA = 120 ohms.

I think another common approximation is VGS(off) / IDSS which can be pretty close.

Thanks for that explanation.  In your example, you ended up with 120 ohms. You have called this a "source resistance" which I have assumed to be the resistance between the source leg of the FET and ground. Have I got this right so far?

If this is right, how does it translate to this particular (schoeps) circuit where you have a 2k2 (or 2k) resistor and a (1m) pot in parallel connecting between FET source and ground, with a 1G resistor connecting the wiper of the pot to the gate of the FET? I mean, if the source resistance happened to compute to 120 ohms as in your example,  does that mean you want there to be (a) 120 ohms between the fet source and ground or (b) 120 ohms between pot wiper and source leg or (c) 120 ohms between pot wiper and ground or... something else?
 
My Yahoo MicBuilders article describes all this in detail with step by step testing, diagrams etc.

Jonathan_D said:
Matador said:
If you can measure VGS(off) and IDSS, you can get very close to an approximation of the source resistance.  You need to remember that you want equal current swing between cutoff (0mA), and IDSS (which can vary wildly from FET to FET, and there may even be several bands to select from even within a single part number), which turns out should be IDSS/2.

My favorite way:  measure IDSS, then calculate IDSS/2.  Ground the gate, connect the drain to some positive voltage: say 9V.  Then use a constant current sink and trim it to IDSS/2.  So if your FET measures IDSS of 5mA, you trim your CSS to 2.5mA, and connect it to the source terminal.  Then measure the DC voltage on the source terminal:  since the gate is grounded, it represents the VGS bias needed to flow IDSS/2.  Then the source resistance is just VGS(2.5mA)/IDSS/2.  So for an example, if it takes 0.3V to flow 2.5mA, then then source resistance would be 0.3V/2.5mA = 120 ohms.

I think another common approximation is VGS(off) / IDSS which can be pretty close.

Thanks for that explanation.  In your example, you ended up with 120 ohms. You have called this a "source resistance" which I have assumed to be the resistance between the source leg of the FET and ground. Have I got this right so far?

If this is right, how does it translate to this particular (schoeps) circuit where you have a 2k2 (or 2k) resistor and a (1m) pot in parallel connecting between FET source and ground, with a 1G resistor connecting the wiper of the pot to the gate of the FET? I mean, if the source resistance happened to compute to 120 ohms as in your example,  does that mean you want there to be (a) 120 ohms between the fet source and ground or (b) 120 ohms between pot wiper and source leg or (c) 120 ohms between pot wiper and ground or... something else?
 
Oh dear I do feel a fool... I missed that article when I looked in your files and downloaded the FET biassing siliconix article instead, which was somewhat over my head. Thanks Ricardo, I will read your FET BIAS article. Much appreciated.
 
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