Noise Contribution Of Floating Cascode Circuitry

Hi

Working on another iteration of my discrete transformerless mic pre; right now one half of the frontend looks like this: [removed]

Q1 is a low-rbb part. Gain is adjusted between 0 dB and 44 dB.

It looks to me as if Q4 does inject some current noise into the feedback network and thus significantly worsens the noise figure at low gains. Is this true? If yes, any fix?

I want to cascode the input transistor for better CMRR and lower capacity/higher speed.

Thanks!
Samuel

If you get your low gains by making Rshunt bigger then you will be getting more contribution from that Q4 current noise. But as it stands now the current noise of the 100 ohms is much larger than the shot noise in the base current of Q4---12.9 pA/rt Hz compared to 500 fA/rt Hz or thereabouts. The other contributions are Q4 voltage noise of maybe a couple nV/rt Hz modulating the current through the 4.7k, so only about the same as the base current shot noise, and the current noise in the 4.7k itself, about 1.88pA/rt Hz. Since all of these are (nearly) uncorrelated the 12.9pA strongly dominates.

If Rshunt goes to, say, 1k, then your noise performance deteriorates due to that by itself, but the effect of the current noise from Q4 will still be small enough to barely notice, maybe making overall noise about 10% higher. The "best" thing is just to provide adequate current for the feedback network and leave Rshunt low, but it's painful.

If current source noise were a problem you can make quieter currents with bigger R3, bigger voltage across, and a JFET instead of a bipolar for Q4. The P channel parts will have higher voltage noise so that has to be considered in the estimate, but with large enough R3 this can be made negligible. Also a darlington bipolar will help since it is much closer to unity alpha, though it will not be quite as good as a FET.

Another alternative: use a highish pinchoff voltage JFET (gate tied to Q1 emitter) like a 2N4391 or 5638 in place of Q2 and avoid the need for the floating bias altogether. The input C will be a teensy bit larger since the FET won't have quite the low input Z of the bipolar emitter, but it will do most of the job of reducing input C.

Thanks--I like the one with the self-biased FET. Improves performance, lowers parts count--that's how good ideas should look like! :thumb:

Samuel

> Q4 does inject some current noise into the feedback network and thus significantly worsens the noise figure at low gains. Is this true? If yes, any fix?

Yes, but does it matter?

Here, Q4's voltage noise is multiplied to the output by about Rfeedback/R3 = 1K/4.7K = very small.

Note that Q3's voltage noise is multiplied to the output by about Rfeedback/R1 = 1K/360 which will exceed the noise contribution of Q1 when Rshunt gets over ~360 ohms.

As a general thing, you have noise sources that vary with gain setting, and noise sources that are constant at any gain. You can reduce these to input noise (times gain) and output noise (present even when gain is small).

Hm, second stage noise contribution is still a mystery for me. :?

So I would better use a resistive collector load for Q1/Q2 if I cared about noise?

Samuel

A resistor is always quieter than a current source given the same available voltage and for the same current. But minimizing noise isn't everything.

BTW I neglected the biasing diodes' noise in the discussion of the auxiliary current source noise, although it's on the same order (roughly two r.m.s. contributions of the "half-thermal" of each one's slope resistance) as the transistor voltage noise. And as seen the dominant noise is that from the 4.7k itself, which is still pretty small.

But minimizing noise isn't everything.

Click to expand...

What are the disadvantages of the resistive collector load in this application? Tempco seems to be OK, I get less than -10% for +30 K.

Samuel

[quote author="Samuel Groner"]

But minimizing noise isn't everything.

Click to expand...

What are the disadvantages of the resistive collector load in this application? Tempco seems to be OK, I get less than -10% for +30 K.

Samuel[/quote]

If the input Z of the following stage is low there's no gain advantage. Power supply rejection is better.