Ron Mancini JFET-based gain control circuit

Svart and all,

I saw a lot of interest in JFET gain control methods over in the Time constants thread, and thought I'd throw this in FWIW.

I suppose everyone here is probably already seen this variation on JFET gain control by Ron Mancini from EDN in 2001, but just in case

http://www.edn.com/contents/images/120601di.pdf

It is a shunt to ground feedback attenuator variation. I searched the forum under Mancini and didn't find a reference anyway. I'm new so apologies if it's old hat.

I think it is supposed to reduce the signal voltage across the JFET to lower distortion without compromising noise so much, so I suppose it could be a alternative approach.

I wonder how it would sound in a compressor when overdriven on a peak compared to the 1176 approach (assuming the linearizing signal was properly buffered to keep the control voltage from popping)?

I'm curious if anyone has any opinions about the merits (or lack thereof) of the circuit they'd like to share?

:thumb:

[quote author="mr coffee"]I think it is supposed to reduce the signal voltage across the JFET to lower distortion without compromising noise so much, so I suppose it could be a alternative approach.
[/quote]Hi,

It'll have those benefits but it isn't new.

> shunt to ground feedback attenuator

Anything with more than 3 resistors in the gain equation makes my head hurt.

OK, I got a clue. "-36" on the chart does NOT mean -36dB, but a gain of 36, inverting.

If the FET is cut-out, obviously it is unity gain (inverting assumed thruout).

If the FET is dead-short, the input is attenuated 10:1 = 0.1, but the feedback is attenuated to infinity, the opamp runs at infinite gain, and 0.1*infinity is gross clipping. With some small resistance in the FET, overall gain is huge. Assuming R3=25K and FET=75Ω, the input is attenuated 10:1, the output is attenuated 300:1, overall gain is 30, except the FET is a mutual coupling which gives (Mancini says and I accept) 37.

We have two "fixed" gains. The maximum gain is, with these parts, 36, and a function of the FET. The minimum gain is unity, fixed by resistors. Nothing the FET can do will reduce gain any further than unity. For limiters we like (but can't generally get) gain-cells that will try to reduce over-large signals, because even a badly distorted limiter overload may be less problematic than a speaker or transmitter overload. But if we have enough maximum GR, this may not be a problem.

I have feeling that noise may be high at some point in the range, but am not prepared to defend that.

The plotted Vgs/Gain curve sure looks linear enough to use feed-forward.

I think its real niche is as a controlled-gain amplifier, bringing small levels up larger but not too large. A mike preamp with DC gain control.

Hmmmmm.... with the assumptions that lead to Gain = 1+((R2||R3)/Rfet), and an assumption that R3 (24K) is much larger than R2 (3K), then the gain is nearly R3/Rfet plus one.

The notion of changing the ratio of Ra Rb to change the slope of the transfer function is dubious. The ratio Ra Rb must be 1:1 to null distortion on a symmetrical FET (and all JFETs are symmetrical enough that the optimum is always very nearly 1:1). If you want to fiddle the slope, put a low-Z or buffered voltage divider in front of Rb.

If the FET is dead-short, the input is attenuated 10:1 = 0.1,

Click to expand...

I dont think this is quite right PRR..... We have a simple 'virtual earth' amplifier here, with its feedback being fiddled with. All the time there is sufficient feedback to keep it operating within its own open-loop gain range, then the voltage at the -ve input is, by definition, zero.
The noise may well be compromised by a factor of 10, but the gain stays the same.

Thanks for the feedback folks.

Hi PRR,
PRR said

Assuming R3=25K and FET=75Ω, the input is attenuated 10:1, the output is attenuated 300:1, overall gain is 30, except the FET is a mutual coupling which gives (Mancini says and I accept) 37.

Click to expand...

Umm, I followed everything said until we get to "the FET is a mutual coupling" part. Would you care to explain what that means when we're not talking magnetic fields? :?

I agree heartily that this is not a good "limit large signals VCA" circuit, but for a low level AGC preamp\compressor\limiter, looks OK then to you folks?

Hi Ted,
I think PRR was thinking out loud in analyzing the circuit under various limit conditions. There are no dead-short zero ohm JFETs, which I'm sure everyone here knows. I'd say you're both right - if the JFET was literally a "short," the op amp would be open loop, and gain would be the open loop gain of the op amp ("infinite"), and the circuit becomes a comparator. But as long as the JFET has some minimum resistance, the circuit is closed loop and the inverting input is a virtual ground which is at zero volts, as you point out.

I suspect the noise gain would be less of an issue than the DC offset voltage with the JFET channel resistance really low, although I suppose other folks who understand that far better than I might know how to figure that. The JFET is kinda near the summing node, and hanging a resistor to ground off the summing node does increase noise gain, so maybe your suspicions are right. Anyone know?

Hi Clintrubber,
you said

It'll have those benefits but it isn't new.

Click to expand...

Would you care to share the circuit you've seen it in? How was it used? How'd it sound?

Thanks again for the informative and stimulating discussion!

[quote author="mr coffee"]
Hi Clintrubber,
you said

It'll have those benefits but it isn't new.

Click to expand...

Would you care to share the circuit you've seen it in? How was it used? How'd it sound?[/quote]
I first saw it in what was also the first 'FX-like' thing I built: a feedback compressor-pedal. I'll try to find back the schematic, it was about the same topology. I didn't think it really sounded good, but that will about totally been caused by my inexperience in how to set up a compressor.
Like I wasn't prepared for the very action of a compressor (robbing attack, which I didn't like :wink: ) etc.

I don't recall if there was a // resistor to the JFET.

Regards,

Peter

I'm skeptical that this circuit offers any substantial advantage from a noise and distortion perspective over the traditional one he compares it to. The noise gain is still large. The article has a glaring paucity of such data, and I don't have the time for a thorough analysis right now :sad:

Possibly the elimination of common-mode swing in the opamp would be an improvement in some apps, and the particular gain law helpful.

Agree with PRR that the use of the control input-drain feedback voltage divider to change the gain law is "dubious"---the improvement in distortion is dramatic with the ~1:1 ratio, and you don't want to mess with it unless you are after effects and coloration. And remember that second harmonic distortion entails a d.c. shift term, although usually highpassed out further down the line---in fact I think some people like the bit of thump and the sense that the world's hinges are rattling a bit when they hear something with a lot of second.

On the subject of FET variable gain circuits: Brad Plunkett told me that one of his early-days home runs at UREI was to fiddle with the existing FET limiter and add additional bootstrapping, allowing the levels to go a little hotter for the same distortion limit, with consequent improvement in S/N. He wasn't that impressed because it was only a few dB, but it made a bit of a stir and put his stock up. I don't know the number of the beast* but I'm sure someone here could identify the relevant schematic and parse out that feature.


*yes I know---and no, in this case it is NOT 666 :razz:

> The noise gain is still large.

Big hit in gain-bandwidth too. At overall gain of 36, the feedback loop is gain of 300. If we take a 3MHz opamp, the bandwidth for a straight gain=30 amp is 100KHz, for this topology only 10KHz! This poor leverage seems to get worse the more we increase maximum gain (and depth of possible GR). The closed-loop bandwidth gets better very fast as we go into GR: 30:1 GR is ~unity gain and 1.5MHz closed loop bandwidth. That has an odd effect: the bottom of the AM radio band is low at idle and rises as we limit. The ball-game pops-up when the studio singer screams.

There is a lot of leverage happening. It ought to be good at something. So far, I don't quite see how the noise and distortion are any better than a 1176-type R-FET divider plus a low-noise amp. I get the same general result for my 2-FET gain cell, a result that looks about 20dB worse than a medium vacuum tube in the same plan.

What we need are high-current LOW Gm devices, but there is no other market for such things so nobody is going to make one. I'm really amused by the type '35/'51 tube, the readily available rip-off of the first remote cutoff tetrode, with "bad" 1935-like performance.

> Anything with more than 3 resistors in the gain equation makes my head hurt.

Hurt so bad, I tried SPICE.



This is a DC sweep analysis: saves a lot of simulation, rectification, time-constants, and is valid because the amp works the same DC or audio.

V6, green trace, is the input, swept from zero to 10V, just like a singer who gets louder and louder. The -1 inverter mostly gets the graph to come out nice.

When the Output, yellow trace, exceeds 4.7V, D1 drives the -4 gain stage and shoves the FET gate negative (an N-channel FET was handy) which turns the FET off, reduces amp gain. Increasing the "-4" to -1000 gives a sharper corner. Note that when input reaches 4.7V, the amp is at unity gain and can't go any lower, output rises again.

FET small-signal resistance is the blue plot. My JFET went down to 130Ω, rises above 35K.

Red plot is FET drain-source voltage, and seems to always be 1/10th of input voltage???

Unlike a 1176, which has near-constant Vds while limiting, this has low Vgs (~30mV) at threshold, high Vgs (300mV) at max GR. THD is not a clean function of Vgs, but this suggests low THD at limiting and rising THD when you slam it, which may be musically useful.

Hi PRR and all,
Interesting way to analyze the Mancini circuit using a DC sim.

Unlike a 1176, which has near-constant Vds while limiting, this has low Vgs (~30mV) at threshold, high Vgs (300mV) at max GR. THD is not a clean function of Vgs, but this suggests low THD at limiting and rising THD when you slam it, which may be musically useful.

Click to expand...

Meaning some soft clipping or rounding of the waveform when driven close to maximum gain reduction?

It's surprising to me that the circuit could have fairly modest distortion (with a higher bandwidth and voltage op amp) at an input level as high as 4 volts. Perhaps the DC analysis is throwing me - is that 4 volts pk-to-pk or 8?

Thanks again for your analysis.

Has anyone actually figured out how to compute the noise gain of this circuit? I haven't got a clue. :?

> It's surprising to me that the circuit could have fairly modest distortion... at an input level as high as 4 volts.

It isn't the level at the input, it is the level at the non-linear parts. In general we could design an amp for any voltage, but high-gain FETs "mis"-used as resistors all seem to get kinked at around 100mV peak. The linearity is also a function of Vgs and the graph wanders all over the place. I won't believe this is a sure thing without more study.

Yes, this is looking like 5V peak. If elaborated with the rectifier and filter needed to handle AC signal, that is 2.8V RMS.

Also we could scale the voltages to any ratios. Mancini assumed 5V peak output, and I just copied his values with a 4.7V threshold. Using his formulas (right column) we could scale to 100v signals yet stay down to 100mV on the FET. (I think that may lead to insane noise gain; no, actually I think the total dynamic range is pretty much a function of the device, and we can scale that to our convenient signal levels.)

Note that the values I picked (part Mancini, part random FET model) only give about 25dB working range between threshold and loss of control. True, many classic limiters do no better, though some of them will at least limit with high THD rather than let the output soar (we could add clippers).

> Meaning some soft clipping or rounding of the waveform when driven close to maximum gain reduction?

No, I don't actually know how an FET goes non-linear. From curves I'd guess asymmetrical rounding, but other folks here have 'scoped hard-worked FET limiters and would know better....

Wait: if the R-FET limiter goes round, this will pop-up the peaks. Remember that this works backward from a "passive" R-FET gain reduction scheme, since the FET is in the feedback side. So it may get very nasty above 100mV at the FET. My analysis would not show this, since it may be using a small-signal value for FET resistance, and certainly is not simulating both sides of an AC wave. (An implicit assumption is that the FET is symmetrical: it is pretty close for small signals but not when we get into distortion.)

I have also ignored the gate voltage divider that low-THD FET gain-cells need, to reference the gate drive to the middle of the channel and null the gross asymmetry of unipolar control voltage on the gate and bipolar signal across the channel.

I think I know how to get a simulated number for noise-gain, but my SPICE makes my mouse-arm numb so not tonight.

The noise gain, as the amount by which equivalent input voltage noise is amplified at the output, is just the gain when the circuit is driven from the noninverting input. Think of the circuit as an op amp output at the junction of the two R's and the FET, and then note how hard the actual op amp has to work to close that loop driving 24k. If the FET R is small relative to the other R's then a pretty good approx is to assume the gain is one plus the ratio of 24k to the FET R, then times 1 plus the ratio of 3k to 27k (a small effect). For a FET R of 100 ohms the noise gain is about 48.6dB (or numerically about 269).

Meanwhile for this example the signal gain is 28.8dB (times ~27.5).

Notice as well that the attenuator of the feedback R/FET R makes the noise of the 3k R more important. I'm fading fast but I get this contribution as a bit larger than the voltage noise one from a better-than-recommended 5nV/root Hz op amp. For the rms sum of the two I get 306uV rms in a 20kHz BW, for a halfway respectable but no writing-home-about S/N with a +/- 15V output swing of about 91 dB---this from just two of the noise sources.

> S/N with a +/- 15V output swing of about 91 dB

OK, but Mancini's values were computed for an arbitrarily-low Vds at +/-5V output, so we should derate your values 9.5dB, or 81.5dB S/N.

This is generally true for the R-FET attenuator too. Series resistance say 33K; thermal noise of that plus amp noise around 5uV, max FET voltage say 100mV, 86dB S/N. That's typical for older JFETs with fairly high minimum Rdss; newer ones have low Rdss so we could use a smaller series resistor, but I have a strong feeling the maximum Vds for specified THD is also lower.

A vacuum tube vary-Mu limiter also has several uV of input noise, but the max input signal can be over a volt. Input dynamic range can be over 120dB, but this is reduced by the amount of GR required

I had no business spending the time, but I got some interesting results doing various distortion analyses of Mancini's and the conventional circuit. I will share them in time, when I understand them.

And yes, the high gm parts probably don't work well for distortion (and so saith the Siliconix folks iirc).

Sims indicate the high-gain low-pinchoff-V parts are in fact terrible for FET compressor/limiter apps. A promising part which is also second-sourced by Linear Integrated Systems* is the Siliconix/Vishay VCR11 dual. Vp is 8 to 12 V (i.e., a lot).


*from whom I receive no promotional considerations, and with whom I've had very limited experience :razz:

The 525 used a VCR2N. The topology was a bit different.
http://www.danalexanderaudio.com/ApiInfo/525Cschem.jpg

> The topology was a bit different.

Basically the same as the antique National Semi paper FET vari-gain amplifier. (5 MEG PDF, sorry!)

Hi bcarso,

Sims indicate the high-gain low-pinchoff-V parts are in fact terrible for FET compressor/limiter apps.

Click to expand...

Seems like somebody told me that JFET Spice models were not supposed to be well-enough modelled for use in evaluating their performance in this kind of application. Have you had sucessful experiences in the past comparing JFET simulations to actual distortion performance in this sort of application ?

A promising part which is also second-sourced by Linear Integrated Systems* is the Siliconix/Vishay VCR11 dual. Vp is 8 to 12 V (i.e., a lot).

Click to expand...

Thanks for mentioning that part. The "antique" AN-129 prr mentioned says positive things about JFETs with high Vpinchoff in these sorts of applications. :green:

[quote author="mr coffee"]Seems like somebody told me that JFET Spice models were not supposed to be well-enough modelled for use in evaluating their performance in this kind of application. Have you had sucessful experiences in the past comparing JFET simulations to actual distortion performance in this sort of application ?
[/quote]

I once tried to make a 'quarter-square" multiplier out of some short channel parts and they didn't work well at all. I could go back and see if the sims predict the poor behavior (the experiments were done in my pre-sim days). The power law was more like 4th or 5th instead of the square law just about everybody uses. I looked at a bunch of other potential errors and assumptions I could have been making and still concluded that the standard formula was wrong for the SK170. Maybe if I had tuned the drain-source voltage downwards I could have found a spot in the transition region that would have worked.

I suspect the stock models probably aren't too bad for the long channels and high pinchoff voltages, but I will find out. Since you started this thread I have gotten some very promising sim results with some topologies I haven't seen before, enough to motivate me to do some actual construction, time permitting.

The way-below-pinchoff behavior is supposed to be governed by the simple equation in the Nat Semi ref that PRR posted, but only for really small voltages. But there has been so much work lately with subthreshold modelling (vide Carver Mead et al.) that I imagine there are some pretty good models out there now, although not necessarily in any packaged spice programs.