Stray Capacity From Track To Ground Plane

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Samuel Groner

Well-known member
Joined
Aug 19, 2004
Messages
2,940
Location
Zürich, Switzerland
Hi

Could someone give me a rough number for the stray capacity per length I have to expect from tracks to a ground plane (one or both sides of the track) on the same layer? And what about capacity to a ground layer on the other side?

Let's assume standard board thickness and material, 10 mil tracks and 10 mil clearance.

Thanks!
Samuel
 
Obviously C = epsilon*A/d, but what's the effective epsilon of 'PCB-stuff' ?

But I guess that for typical traces the parasitics (the sideeffects) will be the most determining. Do you have the possibility to just measure a typical stretch of such a construction ?
 
Obviously C = epsilon*A/d
It is not clear to me if the plate capacitor formula is a good approximation, as one "plate" is much smaller than the other. In the case of side-to-side tracks the area A seems to be rather ill defined.

I didn't understand what you mean by "parasitics"?

Do you have the possibility to just measure a typical stretch of such a construction?
Hm, I think I'd have to order a special PCB for this. My DMM seems not to be capable to measure anything below a few hundred pF with reasonable precision so it would need to be a rather long trace.

But there must be some RF designer around who has written down his rule-of-thumb, no?

Samuel
 
[quote author="clintrubber"]Obviously C = epsilon*A/d, but what's the effective epsilon of 'PCB-stuff' ?

But I guess that for typical traces the parasitics (the sideeffects) will be the most determining. Do you have the possibility to just measure a typical stretch of such a construction ?[/quote]

Something around epsilon_r = 4 ... 4.5 if you're using FR4.
(epsilon = epsilon_0 * epsilon_r)

JH.
 
[quote author="Samuel Groner"]And what about capacity to a ground layer on the other side?

Let's assume standard board thickness and material, 10 mil tracks and 10 mil clearance.[/quote]

A trace running over a ground plane is a microstrip. Normal PCB thickness is 1.6mm; normal copper foil thickness is 35um (for 1oz copper); 10 mil = 0.254mm; E(r) for FR4 is ~4.2. If I didn't screw up the units, the trace capacitance wrt the ground plane should be ~ 40pF/m.

No idea about the capacitance between a trace and a ground plane on the same layer; maybe the formulas for parallel differential traces can give you a first-order answer.

Resources:
http://www.technick.net/public/code/cp_dpage.php?aiocp_dp=util_pcb_imp_calculator
http://www.ultracad.com/calc.htm (have a look at their Tech Notes as well, lots of useful info).

Hope this helps,

JDB.
 
[quote author="Samuel Groner"]
Do you have the possibility to just measure a typical stretch of such a construction?
Hm, I think I'd have to order a special PCB for this.[/quote]

You can always use the method described in http://www.sigcon.com/Pubs/news/6_08.htm . Build a model which is 100x (or any convenient factor) larger than the actual PCB, and measure on that.

For example, on a PCB, copper thickness is around 35um. So find some 1mm thick sheet metal (=30x 35um), cut off a 'trace' 7.5mm wide, position it 7.5mm from the rest of the sheet (the plane), measure the capacitance and scale accordingly. Don't forget to get some base material with an E(r) around 4..4.5.

All this will give you a (reasonably accurate) estimate; if you need precise figures then you either need to build the PCB and measure it, or invest lots of $$ in a 3D waveform simulator. Keep in mind that the physical properties of a PCB will vary between board production runs, and that temperature and humidity have a measurable effect on E(r). IME, you can expect tolerances in the capacitance between 10 and 50%.

JD 'insomnia' B.
 
I bet you do not need an exact answer. PCB capacitance will normally be small compared to device capacitance, and you are smart enough to layout any C-critical nodes as small as possible. You just need an order of magnitude: 0.5pFd or 5pFd?

I was going to say that most insulators run 3 to 10 times the capacitance of a vacuum, but JH gives FRP = 4.0-4.5 which seems fine to me. Thanks, JDB, for the links; and Welcome.

> It is not clear to me if the plate capacitor formula is a good approximation, as one "plate" is much smaller than the other. In the case of side-to-side tracks the area A seems to be rather ill defined.

I bet you can solve this near-enough with over-simplifications.

When one plate is so wide and the other is infinite, clearly the area under the trace adds a lot, the area far from the trace is negligible. Say the trace acts twice as wide as its actual width.

For side by side traces: you have the edge-area which is small but also small-distance, and the "top" areas which are large but further apart. Compute the edge area and distance, assume the e is about 4, find that capacitance.

For the "top" and "bottom" capacitances: draw a bunch of circles representing the electric field. Find the average path length. Use that and the area to estimate the "top" capacitance, which is effectively in vacuum. Multiply by 4 to find the bottom capacitance, since most of the circles will be inside the FRP. This answer is surely wrong. You can divide the traces into infinitesimally narrow strips and compute each one with calculus. There is probably a simple universal answer for infinitessimal space between strips. But the rough answer is probably good enough for your purposes.

It can matter. At MHz, surface mount has advantages in part because of smaller stray PCB capacitance. But I think if you have to ask, a rough answer will focus your attention on where it matters and where it can be ignored.

You could also build an RC oscillator with CMOS, big R (like 100K), top-accuracy 10pFd caps paralleled with a few inches of trace capacitance. Measure the oscillation frequency, use a knife to cut-out the trace-caps, measure again. The change in frequency is proportional to the change of C. The C is not known exactly: 10pFd parts may be +/-1pFd and you have unknown stray pin and pad capacitance. (In theory you can use the R to compute what the frequency "should" be, and know the true capacitances; CMOS is not that precise and a precision oscillator for very small C is not easy.) Air-wire as much as you can, to stay off the hi-e FRP.
 
PRR, thanks for your writing.

I bet you do not need an exact answer.
True. The trigger for my question was a simulation showing that even pretty low capacity values shunting the current source of a differential input pair seriously degrade CMRR. I believe that the CMRR simulation of a standard SPICE implementation is not very trustworthy (i.e. they forgot nonlinear capacity and transistors are perfectly matched). Nonetheless it is good to have a rough estimate on how carefull one needs to be when laying out the PCB.

Samuel
 

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