Matching FETs...again

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byoung

Well-known member
Joined
Jul 16, 2006
Messages
125
Location
San Gabriel Valley, CA
matching is very time consuming... if you touch one transitor the value changes to +/- 10% so you have to wait some time until the measured value has stabilized... if you preselect your transistors by measuring the hfe with your multimeter you'll save a lot of time...

that method worked very well for me...

Set up a test rig similar to the actual circuit:


R1 should be equal to the series resistor used in the actual limiter.

V4 is a DC or AC source. It must be 100mV peak or less to stay within the FET's triode range. A 1.5V battery and a voltage divider to give 100mV will work. Or use an audio signal generator set for about 70mV RMS (100mV peak) output. Read the voltage from ground to the "V" symbol. For the DC source, you need a DC meter that will read 100mV down to a clear indication of 10mV; a 199mV digital voltmeter is barely good enough. For AC source you can read the output with a high impedance ACVM, or a high impedance audio amplifier (direct-box into a mike input) monitored with a VU or PPM meter. The audio technique can read in dB, which is intuitively what we want.

V1 is a 9V battery and a pot so we can put 0V to -9V DC on the Gate. Put a good DC voltmeter on the Gate.

Start without the FET. Trim your source so you get 100mV DC or 70mV AC at the "V" symbol. If you are using a VU meter, first use an ACVM to confirm about 70mV AC, then trim the mike amp so the VU meter reads 0 VU.

Put in an FET and trim the Gate voltage to -9V. You should still have the same voltage at "V". If not, check your connections.

Now trim the Gate voltage toward zero, slowly. Watch point "V". At some point it will drop 10%: 90mV DC, 63mV AC, or -1VU. Write down the Gate voltage needed to make this happen.

Now find the Gate voltage to make point "V" 50% or -6dB.

Now find the Gate voltage to make point "V" 10% or -20dB.

Insert another FET. Repeat.

The 90% or -1dB point is the 1dB Gain Reduction point. If you are just trimming a couple dB off the top, this is the most important test.

The 10% or -20dB point is of course 20dB GR. If you expect zero image shift in sustained heavy GR, this has to match very well.

For general use, all three points must match well. Also all points in between, but JFETs are predictable enough that if you match at -1dB, -6dB, and -20dB, it will probably be close everywhere else.
 
I would test them in-circuit, looking at actual GR vs. control-voltage when Q-bias has been adjusted. Seems to be the simplest and easiest (if you remember to put in sockets for the fets)

Jakob E.
 
What would be the correct process for matching the jfets in the 1176 circuit. It looks like this may be the easiest way, I'm just not sure how to do it? What type of input signal(I'd be using Pro Tools signal generator)? At what points do I measure? Should the limiter be compressing or in bypass, and does the attack/release/in/out/ levels affect it?

Thanks,
Brian
 
It´s a joke man. Dont you remember Wile E & the Road runner?
http://looneytunes.warnerbros.co.uk/web/stars/stars_wile.jsp
 
Does this help?..................look here under JFet matching
http://www.geofex.com/

About 1/3 down the page,date 04/16/02
Aharon
 

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