[quote author="bcarso"][quote author="clintrubber"]Adding groundplanes for circuits with Hi-Z nodes _could_ influence bandwidth to some more or less noticable degree if the line to plane spacings etc are small. But it won't happen right away.
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So---for high-Z nodes be wary not only of the magnitude of the stray capacitance but also its quality, and try to minimize the potential effects.[/quote]
If the nodes are that sensitive, the best thing to do is "guard" that pin by surrounding it with the ground trace. Most data sheets will provide application info that shows ho to do this.
One of the more important things that Tek learned, besides the inter-electrode capacitance and dielectric absorbtion problems with some board material, is that distortion in circuits was greatly affected by the symetry of the layout. This is very important in pattern layout of balanced inputs, and a lot of routing programs do not have design rules to make sure the layout keeps things balanced. Most of these programs make the design "pretty". That is why experienced designers usually have to finese the design when the layout program is done.
Board quality can vary, but if you are using stock from someone like Rogers, they are pretty consistent. There is some good pdb layout info on the internet, and also in the usenet group Alt.Binaries.ebooks.technical.