bcarso
Well-known member
Has anyone had experience with equipment where occasionally current flows into forward-biased protection diodes on pins of CMOS parts? Specifically, I have a horribly complex EQ with tons of 4016 quad bilateral switches in design/breadboard/layout. In order to preserve dynamic range I am running the 4016 parts off of +/- 7.5V, and the opamps from +/- 15V. The switches are positioned at the inverting inputs of the opamps to minimize the voltage swing across them and hence minimize distortion.
I'm using 4016 parts because they are cheap and because they don't have the nasty behavior of 4066 parts when switching, which would require a preemptive muting function every time some setting was changed.
Under high level drive there are times when the unselected switches see more than |7.5| volts. But it is always with a resistor in series to limit current, typically less than a milliampere.
Right now I have belt-and-suspenders clamping with SOT23 dual diodes at each affected node, clamping to lines positioned 0.7 volts below Vdd and 0.7 volts above Vss. For one channel this entails 76 duals!
When I test a candidate 4016 with my Fluke DMM in the diode mode, which pumps 1.0mA into the DUT, I see voltage drops from given pins of the 4016 to each supply pin in the neighborhood of 0.65-0.73 volts. So these clamp diodes are not large, nor would one want them to be for other reasons. The question is: would there be any long-term degradation effects from repetitive forward conduction?
Of course the power supply for the CMOS needs to do a good job regardless of the polarity of its output current, since the nominal small leakage current under static operation will be tiny compared to the reverse-direction clamp diode conduction currents.
I can test this in short term, and even determine what current reliably damages a part, but it would be nice if someone has had experience already. Datasheets are not very helpful, as in most cases they never specify a current, and assume a voltage source and tell you to stay away from anything more than 300mV above Vdd/below Vss.
Also, with some CMOS, there are parasitic bipolars that can be triggered into conduction with a suitable transient and work as silicon-controlled rectifiers, and suddenly put a clamp with about a 1.2V drop across the power supply rails.
Seems to me Pease said something about overload of CMOS gate inputs once, when showing some pulse generation circuits where a capacitor slammed the input during switching. But I think he was just wary, said you shouldn't do this, and didn't give any limits.
I'm using 4016 parts because they are cheap and because they don't have the nasty behavior of 4066 parts when switching, which would require a preemptive muting function every time some setting was changed.
Under high level drive there are times when the unselected switches see more than |7.5| volts. But it is always with a resistor in series to limit current, typically less than a milliampere.
Right now I have belt-and-suspenders clamping with SOT23 dual diodes at each affected node, clamping to lines positioned 0.7 volts below Vdd and 0.7 volts above Vss. For one channel this entails 76 duals!
When I test a candidate 4016 with my Fluke DMM in the diode mode, which pumps 1.0mA into the DUT, I see voltage drops from given pins of the 4016 to each supply pin in the neighborhood of 0.65-0.73 volts. So these clamp diodes are not large, nor would one want them to be for other reasons. The question is: would there be any long-term degradation effects from repetitive forward conduction?
Of course the power supply for the CMOS needs to do a good job regardless of the polarity of its output current, since the nominal small leakage current under static operation will be tiny compared to the reverse-direction clamp diode conduction currents.
I can test this in short term, and even determine what current reliably damages a part, but it would be nice if someone has had experience already. Datasheets are not very helpful, as in most cases they never specify a current, and assume a voltage source and tell you to stay away from anything more than 300mV above Vdd/below Vss.
Also, with some CMOS, there are parasitic bipolars that can be triggered into conduction with a suitable transient and work as silicon-controlled rectifiers, and suddenly put a clamp with about a 1.2V drop across the power supply rails.
Seems to me Pease said something about overload of CMOS gate inputs once, when showing some pulse generation circuits where a capacitor slammed the input during switching. But I think he was just wary, said you shouldn't do this, and didn't give any limits.