Wordclock amplifier

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10ns jitter -> (105-20*log(10^8)) = -55dBFS
1ns jitter -> -75dBFS
100ps jitter -> -95dBFS
10ps jitter -> -115dBFS
3ps jitter -> -125dBFS

What kind of noise is this? Is it usual noise, white noise? Is it visible on analyzer? Is it present only when there is signal, is it dependent on signal level? Or is it there all the time at same level?

Can I conclude about jitter based on noise level? If yes, this means that If I see no increase in noise level, that means that I didn't introduce any additional jitter? Does it work like this?

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[quote author="gnd"]What kind of noise is this? Is it usual noise, white noise? Is it visible on analyzer? Is it present only when there is signal, is it dependent on signal level? Or is it there all the time at same level?[/quote]
As the earlier thread indicated, jitter distortion is dependent on signal level and signal frequency; higher frequencies are affected more than lower frequencies. What happens is that the frequency spectrum of the jitter (=phase noise) is convoluted with the original signal; the result is that the signal is 'smeared' in the frequency domain. If the phase noise is wideband white noise (which almost never happens) the result is a raised noise floor. In real systems you're more likely to see phase noise with a tent-shaped density vs frequency distribution (as in this article), or with peaks at certain frequencies. This web page gives an (extremely simplified) overview of the impact of jitter. Better information (with a lot more mathematical background) is available in this article.

[quote author="gnd"]Can I conclude about jitter based on noise level? If yes, this means that If I see no increase in noise level, that means that I didn't introduce any additional jitter? Does it work like this?[/quote]
Not quite. What you can do is follow the procedure in Analog Devices AN-501. The problem there is that you need a low-distortion waveform generator as a source. You could substitute a self-clocked DAC, and slave the ADC WC from that, but then you'd still be measuring total system jitter performance, and not just that of your interconnect. Let me know if you want a recipe.

Back to your original question. With minor modifications, this circuit should do what you need:
pnp-difflimiter.png

The transistors can be 2N4403s. Use a regular driver (as described in the earlier thread) instead of the inverter. V+ needs to be low noise, as the PSRR of this circuit is minimal. You may want to include emitter degeneration resistors, to limit the total gain to ~5x. Instead of the potentiometer you could have a servo or an RC filter to auto-adjust the duty cycle to 50%, although with emitter resistors and good thermal coupling between the transistors a multiturn pot is probably good enough for 2Vpp input signals. If you use a clean supply and emitter resistors this simple limiter has pretty good jitter performance.

Video distribution amps work too, if they can handle 5Vpp signals (most can't).

JDB.
 
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