CMOS circuit in pull up and pull down phase simultaneously

This is my first post here yay

Quote:
Notice that a digital CMOS circuit cannot (ideally) be in a pull-up and pull-down phase at the same time, or else both the p/n-networks will fight to keep the voltage on the capacitance either Vdd or ground. The p-type transistor network is complementary to the n-type transistor network, so that when the n-type is off, the p-type is on, and vice-versa.


This is from the wikipedia article on CMOS logic. I am very new to CMOS and am trying to understand it better, and so I have two questions.

MOSFETs are basically switches controlled by an input voltage and CMOS is just a big series of these, right?

And, as you read above, all-knowing wikipedia suggests a way to put one into both pull up and pull down phases (like a switch being both on and off at the same time and fighting toprovide each output with voltage.) If anyone knows how this happens and whether or not this is damaging to the MOSFET or CMOS circuit, I'd really appreciate it.

I really want to hear this happen.

Beware of Wiki facts, they're written by folk like you and me...

Look at CD4007 with some uncommitted devices that can do all kinds of tricks.

"Complementary Metal Oxide Semiconductors"... in general a typical CMOS logic gate is two opposite polarity devices that both conduct if gate input voltage lingers mid supply. Some have even gamed this characteristic to use a CMOS gate as a simple inverter with negative feedback. However be careful when trying to use them this way with too much power supply voltage as the dissipation can get nasty above 5V or so.

JR

> a digital CMOS circuit cannot (ideally) be in a pull-up and pull-down phase at the same time

The flaw in the ointment is "digital". There are no digital circuits. They are analog circuits "always" slammed hard one way or the other. But "always" is pretty useless, we usually want a change some time.

CMOS is made with Enhancement Mode FETs. When Vgs is zero, current is zero; when Vgs rises toward drain, current rises. (All JFETs are made Depletion Mode: zero Vgs is full current and taking gate away from source and drain reduces current.)

Take a classic CMOS chip, the simple inverter. Use 10V supply for simplicity. When Vin is zero V or 10V, one device is on and the other is off. If the load is another CMOS input, the steady-state currents are all zero. Even allowing for leakage, CMOS will run years from teeny battery.

Now put the input at 5V. Both devices are ON.

Why doesn't it burn up?

Standard CMOS is lame stuff. Full-ON is really many hundred ohms, even 1,000 ohms. So 10V supply, 5V input, both devices ON at 1,000 ohms, the total resistance is like 2K, the supply current is like 10V/2K or 5mA, the gate power is like 10V*5mA= 50mW, the package is good for maybe 500mW, it don't fry.

This makes sense (it don't fry). Digital circuits are rated by speed. At maximum speed, the devices are spending almost all their time pulling load capacitance up and down, and on average the output voltage is near mid-way more than at the extremes. To survive maximum speed operation, the device package and device resistance must be proportioned so it don't melt.

What is the output voltage for 5V input? "Not Sure." The N- and P-channel devices are not exact complements. It may be high, low, or somewhere in between.

There's a simple way to force the two devices to equal current and about-halfway output voltage. Connect the output of an inverter back to its input. Remember, it IS an analog circuit. This connection is negative feedback. It will seek the gate voltage which causes equal current in both devices (there's noplace else for current to go). IIRC, it will sit about 6V on a 10V supply: not exact half due to P/N unbalance, but pretty close.

If you try this at higher voltage on the 6-inverter DIP-14 package, it will get VERY HOT. I never melted one on the bench, but I would not mass-produce airplane safety gear this way.

The out-in connection can be a large resistor, since gate DC current is near zero. Now you can build a "linear" amplifier. Cap-couple in and out and run audio in it. RCA had a whole datasheet for such uses. It isn't a terribly good amplifier. However if you have CMOS logic all over the product and need one little linear function, it may be economic.

Here's Fairchild's copy of a shorter Linear CMOS essay.

Note that you can work at 3V supply and get gain over 300! A BJT-resistor amp can only do 100 at 3V. However the 3V Linear CMOS bandwidth is flat only to 100Hz. At 10V-15V, gain is only like 30, but flat to a MHz, GBW 30MHz.

You can try to claim "rail-to-rail output" but this is only true with no load at all. Unless your load is flea-power, there's probably some far better way to swing.

Don't miss CMOS, The Ideal Logic Family. Linear mode is considered "bad" in this paper's context, but they can't avoid touching the "Ideal Logic Family"s true analog nature. Look on page 4, figure 5. (This fig was clearer before it was Xeroxed so many times.) Note that at 15V supply, equal-current (input near 9V), the gate current is 8.5mA, gate dissipation 127mW, +/- wafer tolerances, times the number of gates per package you have wired linear. Gets awful hot. 10V supply is pretty safe, though very un-thrifty.

> new to CMOS and am trying to understand it better

Don Lancaster CMOS Cookbook.

I'll be snarked. It's "in print".

ISBN 0750699434
$40 list, $30 at Amazon.com

Ah, that's the "2nd edition". Also sold as ISBN: 0672224593

I dunno what Howard Berlin could have added which is worth it to a newbie.

Get the First Edition. ISBN: 0672213982

In 1977 it was under $10. (I have a 1st edition 3rd printing.)

ABE.com lists several "good/acceptable" copies at $6-$10 delivered.

There's another CMOS Cookbook by Braga. Never saw it.