Promising series on decoupling/bypassing

This looks worthwhile, based on this first installment:

http://www.audiodesignline.com/showArticle.jhtml?articleID=206800872

a good reminder that opamps are more than 3 terminal devices.. but keep in mind those dreaded capacitor resonances are at impedance minima...

JR

In the later of the previous four articles, that are mentioned and linked in the first of the new series, if I recall correctly, do show some parallel resonance effects which raise the Z of the given node, sometimes significantly.

Thanks for the heads up, Brad

Promising and VERY relevant. Last week I started a new board design, and Im deep in the power conditioning and distribution part of it right now. the legacy products at my company generally use various board-level switchmode converters which are cleaned up with linear LDOs. one of the parts we use alot of is none other than the LT1761 (the one they use as an example in that article). I was aware of the bumpy impedance vs freq, but reading this has got me thinking about it a bit more.

Ive been working with regulators on and off for the past couple of months for no particular reason. Ive already got simulation models built up for various standard and non-standard topologies. I just had a look at them again. I can improve the flatness of the impedance drastically (and reduce the ringing due to load transients) compared to a 1761 based approach, but the big question to me is, is it worth the effort? My app is the psu for digital control circuitry in some very very expensive mixed signal communications equipment. the budget is there to do a custom circuit. but the existing 1761 topology works good enough*, it is proven, we stock the components, etc. a totally new design would require alot more testing and verification, a new MTBF analysis, etc. is Kendall Castor-Perry just trying to psych us out? what I mean is, how intellectual is all this? 99% of designs out there use the IC LDO approach, warts and all.

Mike p

*although any measurable improvement would be welcomed by management. in the past there were issues with small amounts of "clock signals bleeding into analog stages", which I am convinced was related to PSU impedance.

The author's concerns may be of little relevance to some systems with very good PSR, and could be critical for ones that have poor PSR.

I tend to spend a lot of time now in sim (initially) looking at my circuit's power supply sensitivity, and tweaking things to enhance if it makes sense. This is of course where you really have to know what you are doing in the real world, and not just in the idealized one of the simulator.

In simpler days, before the advent of extensive digital alongside the analog, life was a lot easier.

I didn't get a warm reception when I first offered this here but back when I was looking into such things I noticed that the standard 3-terminal regulators used similar to 741 opamp technology inside so exhibited a similar rising output impedance characteristic due to GBW etc. Shunting the cheap 3 terminal regulator with a properly sized electrolytic cancelled the rising active impedance with the falling reactance based impedance. From memory something like a 1,000 uF shunt gave a nice flat low impedance output for several octaves above the audio band.

Obviously for PS impedance above the frequency where the electrolytic capacitors ESL dominates requires paralleling with smaller better caps. I haven't revisited this since the modern generation of "switcher" electrolytic caps so I suspect that corner frequency is even higher now.

Another consideration, you should be able to predict from the signals coming into a circuit block and environment signals interface with upon leaving, how demanding it will be upon the PS. Front end inputs can be LPF and interfacing with the nasty outside world at final outputs should expect the worst (RF et all).

JR

I, for one, appreciate all the input you are willing to share, john. And I remember you posting that bit about 1000uF electros jiving with 78xx regulators. What I took away from that is the concept of the cap matching up with the regulator. A big, cheap al-elctro has perhaps the "right" amount of ESR in this application. lower Q is not always a bad thing. I wouldnt assume that those new Switcher friendly caps are necessarily going to be better in this application. optimising ESR is also mentioned in the older decoupling series: "Know the sometimes-surprising interactions in modelling a capacitor-bypass network", linked off the article brad posted about.

sorry for my whiney, vauge post yesterday. I am looking for an excuse to not fully open this can of worms right now. Ive got to be careful what I say to the bosses, because I will be expected to follow through if I bring this up.

Mike P

(I understand your dilemma Mike.)

One thing I do a lot when I am wondering how good my regulated supplies are is to make a little pulsed load with a power DMOS FET, resistor, and a function generator driving the gate. I usually use a low-duty-factor pulse and hit the regulator's output with something fairly brutal, and see how things look.

(Of course there are fancy pieces of test gear that you can buy for this sort of thing too).

If it is a premium design of mine the regulator is often at least partially made from discrete components, and I can tweak the compensation as well as the output capacitor(s). It's remarkable how much better the performance can be when optimized.

I used a simpler test when designing PS, I just feed a sine wave current into it through a cap coupled R. ( EDIT: note: you need to be pulling some nominal DC current from the supply for this test to be representative.)

This also gives a fair representation of how the PS impedance varies with frequency by sweeping the sinewave frequency and even linearity by observing the output voltage, while that's a little hard to define what that maens, my assumption is a flat, low, resistive source impedance is good.

FWIW the kind of load variation the PS "should" see in an analog design would be primarily audio frequency. Supplies for digital design will be a somewhat different animal with much higher frequency narrow spikes of current.

JR

[quote author="JohnRoberts"]I used a simpler test when designing PS, I just feed a sine wave current into it through a cap coupled R. ( EDIT: note: you need to be pulling some nominal DC current from the supply for this test to be representative.) [/quote]

I was thinking of using a network analyzer to do something similar. though Im afraid of what I might find.

[quote author="JohnRoberts"]Supplies for digital design will be a somewhat different animal with much higher frequency narrow spikes of current.
[/quote]

Im trying to rationalize this. As I see it the edges of the "square" load pulses have harmonics going way way up in frequency. a digital IC clocked at 20MHz doesn't just dump 20MHz noise on the rails, rather 20MHz and all its harmonics. as far as proper operation of the digital circuitry is concerned, I guess having low-z at the clock frequencies would go a long way. but even then, impedance minimas of a lumpy impedance vs frequency power rail will cause ringing at those frequencies every time a load transient occurs, ie at every clock edge.

my whole reason for getting tangled up with this is the radiation of that noise into the sensitive analog stages. in an audio circuit this could be considered out of band and if each stage was appropriately band limited at its input all is well. but the "analog" section of my mixed signal design extends from 50MHz to 20GHz. IMO $100 worth of machined, alodined, multichamber shield enclosures with ceramic feedthru capacitors all over the place should'nt be needed to get low noise every time we have a micro in the picture.


mike p

Digital logic is pretty tolerant of PS noise but grounds need to be solid. The concept I use to visualize digital noise is small caps alternately connecting to PS or ground. Understand what are the worst sources of this noise (like large memory chips or big proc) and locally provide HF PS caps to provide short term current supply and shunt those spikes locally at device pins. Rely upon PS for average current.

Of course this all easier to say than do.. but care must be used in routing of grounds to keep digital noise out of Audio ground or decoupling caps will couple that noise into an otherwise clean rail.

YMMV

JR

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1100,P1221,D4109

pages 25 and 26

The latest in the new series from Castor-Perry:

http://www.audiodesignline.com/showArticle.jhtml?articleID=206801717