Latest from Castor-Perry on decoupling---end of the series

http://www.audiodesignline.com/showArticle.jhtml?articleID=206905923

I like his suggestion that simulators might feed back to the keyboard and burn your fingers :razz:

(this series is referenced in at least one earlier thread on the subject, and I'm too lazy at the moment to search for it---if a moderator would like to append this to it, and then delete this new thread I should be quite happy)

KCP was an audio guy at TI and Burr Brown for quite a few years... _very_ _very_ knowledgable guy.

The settling behaviour is always better with the larger values of decoupling, up to 470nF. If we're going to be using such large decoupling capacitors, might it be sensible to put an additional small decoupling capacitor in parallel, to take us up to the three capacitor situation discussed in "Know the..."?

Figure 6.12 shows the result of adding a 4.7nF ceramic capacitor (with 0.7nH inductance and 80 mΩ of ESR) in parallel with the existing swept decoupling capacitor. The result is a new, undamped resonance at an even higher frequency, as we'd expect. The extra cap appears to add no value at longer timescales, and just additional ringing in the first few hundred nanoseconds. This points to a preference for a single, well-chosen decoupling capacitor rather than several in parallel.

Click to expand...

the first part of this quote was damn interesting. I know I've been guilty of paralleling up cap values "just in case" on many projects. Caps are cheap, trouble from bad decoupling is not..

As for the second paragraph, I've known for some time that paralleled caps within 100 times of the farad value(of each other) tend to resonate but I had never really stopped to analyze the reality of IF the second cap actually helped and had only assumed that it did since I've seen so many senior guys do it over the years. I might need to take some time on the expensive test equipment at work and actually do some of his experiments and show the rest of the guys. The bean counters are always bugging us to cost-reduce our designs.. Maybe this is the ticket.

I've always used tantalums for design, not because I found them superior, simply because they are nice and small for a given value! Time to revisit this as well. I need to read the rest of the article and then forward it to my director.. He's an old-school engineer with the mantra of "when you think it has enough decoupling, add some more!". If for nothing else, it will make for a good argument.. :green:

EDIT: It also goes along the lines of paralleling up AC coupling caps in signal paths.. I personally have found NO increase in performance using any shunt cap with a quality coupling cap.. Proper cap choice (read: anal) seems to trump any trick and/or gimmick in this field.

PS: Good to see you again Brad, I'm looking forward to reading more of the interesting articles you keep finding!

I only _wish_ I could write articles that good

[quote author="Svart"]PS: Good to see you again Brad..[/quote]
Likewise.

This series is quite good, even if not perhaps the "last word" on the subject. But it is a big step forward, and I do like how it questions the conventional wisdom, and dares support this skeptical heresy :razz: with serious data.

I was just studying a preamp design (Pass Ono*) which has film bypassing of 'lytic coupling caps here and there. It's almost as if an aspiring and properly audiophoolic designer has to incorporate those, lest people complain.

Note that when applied to coupling capacitors, the effects of resonances are to insert dips in the transmission. How serious they are will depend among other things on the impedances on either side.

Maybe there's motivation for concocting nominally capacitive composite networks that are optimized for a given source/load impedance combination.



*service manual here:
http://alexkachler.free.fr/xono/doc/aonoserv0.pdf . Plenty of material for raising eyebrows, but to each his own.

Are any of these resonances below where only bats can hear them... ?

JR

I think maybe the concern (or at least a legitimate reason for concern) is more for things potentially interacting in sampled-data systems, like buffering for A/D etc.

I guess I would also worry a little about IM stuff heterodyning down into the audio band.

Switchmode amps as well open up a whole new vista for ultrasonic crud to be translated into audible artifacts.

Of course a number of problems can be alleviated just with a bit of simple lowpassing here and there, as you and others have pointed out. It's ironic that the subjective impression of getting rid of out-of-band signals that might produce artifacts fron slew-limited or other detection mechanisms, are I suspect perceived as greater high frequency clarity/transparency/"extension" etc.

I forwarded those articles to some of the proponents of the"as many different parallel caps as you can find" guys that seem to think you need 5 different caps of various values to "be certain" to get all those pesky frequencies..

BS! was the resounding reply for the most part, but then I later found that most had not even bothered to read any of the articles.

As time moves on, a few of them have read the articles and agree that most everything in them makes sense. But they aren't budging on their stance.

And the company wonders why we have a large number of spurs that seem to emanate from the power rails...

Distantly related, but from a different specialization than we usually discuss in here, the valiant pursuit of digital ICs to keep Moore's Law alive, comes this piece:

http://www.edadesignline.com/showArticle.jhtml?articleID=207100271

The notation of his scaling laws came out execrably in print, but the text is not too bad, if a bit literary for its purpose. Of course it is a pitch for his sim software, and I have to resist the tendency to hear him speaking like Apu in the Simpsons, but so it goes.

I was pleased that at some point he faces the ultimate need for "current mode" logic and differential structures. It all gets back to the analog domain eventually.

Yup L di/dt...back to a bunch of small caps at every chip, as if that ever wasn't good.

As digital logic goes lower voltage, PS noise is proportionately a larger concern. Hopefully the noise caused by the digital chips will be proportionately lower too. At least the term attributed to voltage swing will scale down. We will still have faster edge rates and more gates to deal with.

Higher performance digital already blurs the line between analog and digital. It seems difficult to ignore one or the other these days.

JR

Interesting stuff.

On a side note, there is an engineer here who designed ICs for IDT for many many years. He has a lot of stories about this but particularly about an ASIC that was designed for a customer and then later released as a product.

At a certain point during operation, with all circuits functioning, this chip could pull something like ~400A+ for some duration. This equated to about 300+ decoupling capacitors peppered on the back side of the PCB just for this chip alone!

He has an acrylic orb on his desk with the first prototype IC encased in it.