Simple XFMR balanced line input stage & DC offset

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Samuel Groner

Well-known member
Joined
Aug 19, 2004
Messages
2,940
Location
Zürich, Switzerland
Hi

For my most recent project, a small headphone mixer, I designed this input stage: [removed]

I'm worried about noisy pots due to the input current. Using U=R*I and the NE5532 data sheet I get 10 mV on the pot, which looks like too much. Is there an easy way to get rid of that offset without a cap and without using another opamp?

Thanks for your help
Samuel
 
[quote author="Samuel Groner"]
Right now I can think of an stepped attenuator only..?

OK, I add "inexpensive" to my wish list... :wink:

I was thinking about a circuit that provides the bias current - John Hardy uses such stuff in his pres (schemo: www.johnhardyco.com/pdf/M1_M2_M1p_20031025.pdf), but I'm not sure how to implement that in my application.

Samuel[/quote]


I was thinking the same way... a trimpot, a cap and a resistot for input current compensation ... I´d try it

steff
 
Why not the traditional input capacitor?

With a 100k shunt resistor after the cap I need at least 1 uF to get perfect freq. response (and I get 300 mV output offset). A 1 uF polyprop is too big for this design. And I want to avoid other cap types. But perhaps you are right, a trimmer is not that smaller...

Anyway, do you think that this
[removed]
might work?

Samuel
 
> Using U=R*I and the NE5532 data sheet I get 10 mV on the pot

How do you figure that?

Frankly, I don't think you have a problem with the original plan. Build it and see before you go nuts with bias-schemes: they mostly just make trouble.
 
[quote author="Samuel Groner"]
R6 can be larger 25K or 50K...

How do/did you calculate this value?

Do I trim R6 by setting voltage across R3 to zero? At least that's what I want...

Thanks!
Samuel[/quote]


most trimpots can take 0.1Watt max power. with your 18V rail and 5K potvalue you have 0.0648 Watt potpower. it should eat that, no problem. but it is not necessary to stress the pot since we have a load of 2Mohm, so even a 100k pot will work fine here.


steff
 
> Using U=R*I and the NE5532 data sheet I get 10 mV on the pot
How do you figure that?

max. input current is 1000 nA, flowing through 10k Ohm -> 10k Ohm*1000 nA=10 mV

Build it and see before you go nuts with bias-schemes: they mostly just make trouble.

Why and how do they make trouble?

The problem with noisy pots is that they only show up after three years...
Samuel
 
> max. input current is 1000 nA, flowing through 10k Ohm -> 10k Ohm*1000 nA=10 mV

Over-simplified.

It isn't 10K: the top of the pot is DC-grounded through the transformer. Assuming the tranny winding is 1K DCR, then the highest possible DC resistance is 11K/4=2K.75.

The other input also has DC error. With S1 open, 6K8 DC resistance. (uh... I've drifted off-topic, because you only care about pot-wiper voltage, but anyway....)

To avoid hard math, let's change 6K8 to 2K75. And assume the pot is stick at the halfway position. If both inputs had the same bias current, we don't need to know the bias current, because it is the same on both sides and cancels. It will never be perfectly the same, but input offset current is usually an order of magnitude smaller than input bias current. According to Fairchild, 10nA typ, 150nA max. Being foolishly optimistic, 10nA times 2K75 is 0.03 milliVolts. 0.4mV is claimed max and should be tolerable.

Ah, but we won't leave the pot at center. If the wiper is grounded, then we have the 200nA typ 800nA max bias current in the 2K75 resistor. 0.55mV typ, 2.2mV max. (Yeah, I remember seeing 1uA on old 5532 sheets, but Fairchild 2002 says 800nA, and I suspect recent production tends to the lower figure.)

OK, if we use your 6K8 with S1 open, and the 800nA max figure, we do have 5.44mV. So it is really your feedback value, not your pot value, that sets offset, as long as the pot-top has that DC path through the transformer.

(Note that at full-up, the chip's 200nA-800nA bias current will mostly flow through the transformer. In this case that is probably a non-issue. There have been cases where larger input currents in smaller cores with more turns caused problems.)

With S1 closed: the DC resistance at the inverting input is 6K81||3K16= 2K16. Or using round numbers: the input error is 1/3rd, but the overall gain is now 3, so the output error will be similar. (However now it balances the 0Ω-2K75 resistance at the pot over most of the pot range, and error reduces to offset current instead of bias current.)

On top of all that you have 0.5mV typ 4mV max input offset voltage error. You can easily end up with a typical sub-mV current error but get a part with 3.9mV voltage error.

In real life: for a one-off, you almost certainly won't get a chip that has the max error specs. It has been decades since I saw even 2mV input offset voltage on a cheap opamp. So build it, if offset looks bad, change the chip, it will probably be fine. Of couse in mass production, you must design so a worst-spec chip will satisfy the customer, because selection or re-work will eat your slim profit.

And the 5532 has been used in millions of mass produced boxes, for decades, with higher value resistors than you propose, without great trouble. Yes, maybe some of the scratchy-pots in cheap gear are due to 5532 bias currents, though I think cheap pots should take much blame.

So my gut feeling is that you won't have a problem. Check the wiper DC voltage, and if it seems high just change the chip.
 
Thanks for your explanation! I knew that my calculation was a very pessimistic worst-case analysis, but did not realize that a typical error will be that lower.
You're comments are very helpful....
Samuel
 

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