Multiplier circuit - transmission-gate trick ?

Something for which the coin doesn't drop at the moment:

Here's a one-quadrant multiplier circuit:



http://www.google.com/patents?id=NwEfAAAAEBAJ&dq=4999521
http://www.pat2pdf.org/patents/pat4999521.pdf

Inputs are the voltage on node A (or the I_0 input-current)
and the voltage on node C.
Current I_2 is the resulting output (or mirrored & then taken from device 8)

So the basic idea is straight on: the opamp makes V_A & V_B equal, so it realizes an output-current that's scaled by device #1 (a FET in triode-region, so a voltage controlled resistor).

But then it goes on by adding device 14 & 16 & the current source 15.
The text states:

The input voltage V_0 is supplied to node C via a transistor 14 acting as a transmission gate element. The transistor 14 is coupled in parallel with a further transistor 16 connected as a diode and supplied by a current I_T.
This configuration allows the voltage V_0 whose value varies between 0 and that of the supply voltage V_DD applied to the second reference line to control the value of the output current at node D in the range between approximately 0 and a value determined by I_0 regardless of the threshold voltage of transistor 1.

Click to expand...

Wrong time of the day here, the coin doesn't drop how that 14,15,16-add-on makes the input-requirement for device #1 more friendly. What's the trick here ?

Thanks / regards,

Peter

PS
Note that the drawing & text mess-up V_D & V_0 a bit, but these are meant to be the same.

> Inputs are the voltage on node A (or the I_0 input-current) and the voltage on node C.

No, the first input IS Io and the second input is Vo.

Point A is derived from difference between I(Q12) and I1 (mirroring Io).

Point C differs from Vo by drops in Q14 Q16.

I'm confused because point C voltage will swing very rapidly at some unsteady point in Io increase. Unless Q12 is a cathode follower? I'm unclear where sources and drains are, who is N or P, what devices are saturated or triode-zone.

Surely the core idea is that if two pairs have the same gate voltage, they have the same ratio of current. Incredibly old.

The key here is working within the variability of the CMOS chip process. (Probably in ways which don't work so well as a discrete assembly of non-matched parts.)

[quote author="PRR"]> Inputs are the voltage on node A (or the I_0 input-current) and the voltage on node C.

No, the first input IS Io and the second input is Vo. [/quote]
You're right, the circuit as drawn (including both 'pre-stages') has those two inputs like you said. I was referring to the core (so that's Fig.1 of the patent), but then I'd better added that pic as well.

Point A is derived from difference between I(Q12) and I1 (mirroring Io).

Click to expand...

That difference will be near zero (assuming the opamp having a FET-input. The pre-stage (on the left) is a I/V-converter: device-12 is in triode-region, and its resistance multiplied by the mirrored I_0 gives V_A.

Point C differs from Vo by drops in Q14 Q16.

Click to expand...

Sequence here was #1 posting, #2 bike ride (15 minutes ) & #3 being pleasantly surprised there was already a response, thanks :thumb:
During activity #2 I realized that device-16 adds VT (plus some bit more: V_GT = V_GS - VT), but that already realizes the claimed 'insensitivity' for the VT of device-1, as in the drop you mentioned.

But I don't see yet what device-14 is doing, maybe some duties for defining the V_D input (a.k.a. V0).

Regards,

Peter

[quote author="PRR"]I'm unclear where sources and drains are, who is N or P, what devices are saturated or triode-zone.[/quote]
As I see it all devices are N-type, except for the two currentmirrors (-13.... & -9 & -8). Different symbols would have been convenient indeed.

Device-12 & -1 in triode-region ('voltage-controlled resistors').
Sources & drains indicated would have been convenient here as well, but we only have to guess for -14 & -16, but while it doesn't matter because of assumed sym., let's say these both have their source to node V_D.

Surely the core idea is that if two pairs have the same gate voltage, they have the same ratio of current. Incredibly old.

Click to expand...

That would be the case when they (say dev-2 & dev-1) would both live in the same regions (like here: http://www.pat2pdf.org/patents/pat5578965.pdf in the figs 17...21 ) but for this multiplier I think the basic idea is a V/I converter (-3, -2) whose ratio is a function of V_A (or I_0) divided by the resistance as realized by voltage controlled resistor dev-1.
Dev-1 & -2 do have the same I_ds indeed, but since -2 is in sat & -1 in triode their V_gs won't be the same.

The key here is working within the variability of the CMOS chip process. (Probably in ways which don't work so well as a discrete assembly of non-matched parts.)

Click to expand...

You're right, this will work decent in an IC, but not as easy 'outside'.


Let's see if the why of device-14 drops into place.
Best I can think of so far is that it's there to help dev-16 if that device under circumstances can't develop its drop of VT + some (VT + V_GS, with V_GS determined by I_T & W/L).


Regards,

Peter

PS Forgot to add to the first post already, sorry for the OT, this isn't directly audio related.