Modular multi channel DIY AD/DA Box

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Well, it acts like a trim. The idea is that you can use that to set the input sensitivity to the value you want and to match hot and cold by trimming. It is not the idea to use it as an volume controller. And however, if you don't want it you can use the resistors on the board for a fixed setting.

Raphael
 
Did I read that correctly? You're doing a master clock as well Rafael? Well, a million thanks for all the effort you have put into this project and a million more for sharing it! ;D
 
hi guys!
i'm following the thread, but i can't really be helpful.
i thought: there's no way firewire is gonna be a solution for this board, too many problems like
gigantic costs, drivers development, chipset costs, and stuff like these.

So, i found this:
http://www.dv247.com/studio-equipment/apogee-x-firewire-x-series-firewire-card--25247
it could be a solution for firewire ( for people like who don't want an adat bridge)
and since it is a solution developed for stuff like Rosettas and AD/DA16x the drivers are gonna be good.
i guess..


what do you think guys?
i don't know anything about power voltages of this thing, but if we can use it we could kick these converters in the High-End sky..
 
I'm actually still working on an ASIO implementation for audio-over-ethernet. So far, I can send multichannel uncompressed audio between two computers and I'm busy trying to tackle latency, synchronization issues and building the configuration UI. Regarding that, there's a screeenshot attached, it's not nearly final since there's a bunch of settings missing for autodetecting devices on the network and selecting the active NICs, but still, I'm pushing this and it will be available sometime in the future (probably a few months away). When complete, this UI would allow you to route virtual input and output channels to remote device input and output channels. Probably without faders, though if there's a need that could be done as well. In software ofcourse.

With regards to a FPGA chip handling the other side of the story, the company I work for is actually a spinoff of a company that does hitech control systems for physics research like particle accelerators. Needless to say, there's a lot of FPGA programming involved, so I'll try to scrounge someone to at least advise on how the FPGA side could be tackled in exchange for free beers and general geekyness.
 

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Hi Raphael!

Your project is really heaven-sent;-) I was really hoping something like that would come up!!
Please correct me if I'm wrong, I'm just thinking loud;-):

I looked over your AD schematic and noticed that you use an attenuator in front of your analog stage.
I think it is unity gain, right? Now the AD should take 6Vpp for 0dbFs or around 8.7dBu.
For me, a good input sensitivity would be 18dBu, so I need 10dB of attenuation. I'd scale the resistors to around 1:3 ratio.
As far as I understand it, those resistors also set the input impedance of the device.
Let's say you are aiming at around 20k diff input impedance that would mean 2*7,5k and a 5k across it.
7,5k==||
        5k
7,5k==||
But those 5k also set the source impedance for your stage to follow, right?
Isn't that kind of high impedance. I'm just wondering if that could be a problem. Isn't it easy to couple noise and capacities affecting the signal due to the high source impedance, or isn't that an issue?
I hope I'm not getting it all wrong ;-)
Best,
Stefan                                                                            
 
Just a quick note: This weekend I've tested the AD-board with an extra oscillator for the system clock letting one AD generate the clock signals for the I2S lines. Worked fine. I'll now have a look wether I can add a little socket to plug in a daughter board with the oscillator on it.

Stefan, I do not expect problems from the trimming because there is the opamp stage between the input and the ADC. And you have no chance. You'll always need an attentuation stage like this to get a signal that is valid for the ADC (except you'll find a good tranformer that reduces the peak to peak voltage).

Raphael
 
Update: I made some minor changes to the ADC-board:
- There's now an additional socket where you can plug in a oscillator daughter board for generating the system clock.
- Some layout changes to minimize the size of the slits in the ground plane.

Raphael
 
No. I was talking about the system clock (MCLK in the schematic). This clock is needed if you want that the ADC is the master of the I2S system and shall generate the bit and the word clock.
For external word clocks you need some additional stuff to drive the clock lines of the I2S interface and the ADC's need to be setted into slave mode.

Raphael
 
rkn80 said:
This clock is needed if you want that the ADC is the master of the I2S system and shall generate the bit and the word clock.

Note that for noise reasons it's better to have the ADC be a slave. As master the transitions on the LRCK/BCK driver lines can couple to the analog part of the chip.

JDB.
 
Hm, recently I read a note that it is better to set the ADC as master: That will improve the system-wide jitter.  ::)
However, using this sockets does not force a ADC to be a master. So you can plug-in an oscillator and still set the ADC to slave. If that is usefull that you've to decie yourself because it depends on your application.

Raphael
 
pietro_moog said:
any news?

It's been less than a week since the last update. Give the guy some time.

rkn80 said:
Hm, recently I read a note that it is better to set the ADC as master: That will improve the system-wide jitter.  ::)

Depends on the scale.

Chip scale: for best jitter performance the ADC(/DAC) should be set as clock slave, to reduce feedthrough and modulation. If the converter chip must be clock master, use series termination resistors and a buffer nearby to reduce the load.

System scale: for best jitter performance the converter box should be set as clock master, as its internal XO clock will have better jitter performance than any recovered clock.

JDB.
 
Hi,

well I have a real life job too with a lot of work. Therefore, the project is sometimes a little bit delayed. Sorry. But here is an update: I now made a box and putting everything together into it. I know from my job that sometimes it can happens when you are making boards with high-frequencies on it that they may work stand alone but when you put them all together they do not work well. So I want to make sure that they can be used to build bigger i/o boxes.
My current configuration is 12 channels in and 24 channels out connected via i2s to a SHARC DSP board.

Raphael
 
Update: Here is an image of the box with 3x the current version of the ADC board in it. The box is not finished yet but it is working, although some things have to be modified and improvised. But that's normal for a prototype... ;)
Some of the modifications will flow into the revision B of the layout and rev.B I'll release for a group buy (perhaps next week?).
The DAC boards will be mounted next to the ADC board and finally I'll make a nice rear panel with cut outs for the plug. Later I want to replace the SMPS by a better one but for now it is ok.

Raphael
 

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Raphael

Awesome stuff and thanks for offering us such a great project.

Can I just raise a query with the power supply? My experience of interfaces that have design imperfections is often related to crappy power supplies. Things that come to mind are cross talk between the ADC and DAC's supplies, not enough voltage headroom etc etc.

What do you intend for the power supply?

thanks
Rich
 

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