Modular multi channel DIY AD/DA Box

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jdbakker said:
What do religious issues have to do with anything? As far as I'm concerned the arguments here are purely technical.

[quote author=http://catb.org/jargon/html/R/religious-issues.html]
religious issues: n.

"Questions which seemingly cannot be raised without touching off holy wars, such as “What is the best operating system (or editor, language, architecture, shell, mail reader, news reader)?”
[/quote]

Perhaps the expression is a bit old school.  ;D

I use my ears for a living; ears are certainly technical marvels but sometimes they like something that sounds less than perfect from a technical point of view.

It's great that you've avoided the lengthy discussion/wars on ext WC's.  8)

Mark
 
Biasrocks said:
Perhaps the expression is a bit old school.  ;D

I'm well aware of the meaning (and of the Clocking Wars), but I wasn't interested in going there. All I'm trying to say is that for a cheap/simple (DIYable) implementation one would most likely have to decide between accurate and flexible. At that stage it might make sense to get an idea of how many people are interested in either before going ahead (or to see if there's a Plan B).

JD "can't get what you want 'till you know what you want" B.
 
JDB, how would you feel about putting together a tiny MCU(or small FPGA)/DDS setup for clock generation?  You could simply have the MCU/FPGA run a state machine looking for key presses and then shift out registers to the DDS that set it up for certain frequencies.  that way you can have a default clock, then with a single button can change clock speeds.

The DDS that I've used is the AD9911 and can do DC-200Mhz in sub-Hz increments with extremely good close-in phase noise.
 
Also,  I haven't really even read this whole thread..  Why not simplify and just use a codec for each channel?  AKM codecs, like the ones used in the Alphalink lineup, are cheap and easy to use with both ADC and DAC on die.

Anyway, this is a cool project.  I wish I had kept up with it and been more a part of it.

 
Svart said:
JDB, how would you feel about putting together a tiny MCU(or small FPGA)/DDS setup for clock generation?

Well...

I've thought about it on and off for some time. I would probably use one of those newer 1GHz SAW oscillators driving an AD9912 driving a bandpass filter with an AD951x clock distributor. Add a microcontroller, a cheap TCXO for an absolute frequency reference (the SAW has good phase noise when compared to the ref multiplier in the DDS, but not-so-great long term drift) and options for digital readout/control. Possibly add a few LVPECL->CMOS translator dongles so you can run a balanced clock to the converter(s) over twisted pair and only go single-ended at the chip's own ground reference. This offers milliHertz-level frequency tunability over a wide range indeed, will VariSpeed all you like, with jitter performance to rival the best canned fixed-frequency oscillators.

However, I don't need one myself, and this kind of tech complexity gets close to 'day job'-levels. Add the fact that you'd need two maybe three complex components in CSP/QFN and home-soldering is out, so someone (ie: me) would have to build and test them. Even at friends-and-family rates the module cost would be at or over $200 (and add up the cost of the major parts I've mentioned earlier and see how close you get...), and at that price I wouldn't blame anyone who pointed out that you can get an entire ADA8k-class converter for the same money.

Or am I being overly pessimistic?

JDB.
[yes, I know the boo-tique CD clock upgrades cost as much and offer way less performance]
 
jdbakker said:
1) VCXOs with a simple PLL. Cheap, best performance, but limited to +/-100ppm tunability.

Not to ruin anyone's party but keeping in mind the general level of this forum, I would choose this option. Easy to get the parts, and least things to go wrong. Because for many, they will.

There are commercial solutions for those who wish for more exotic clocking.
 
Well, I had a varispeed capable soundcard and didn't use the feature at all, not even testing....
In live recordiing, things may be different though...?
Personally I could easily live with 44.1/88.2kHz. I guess lots of people need 48kHz/96khz for compatibility to other gear or delivery formats, too.
I would not need varispeed and be totally happy with option no 1.

(Nevertheless I find the varispeed approach of JD extremely interesting from the technical point of view, maybe because it is far over my head to even imagine what it takes to properly implement such a solution...while he obviously does...)

I also had a head-up when the AKM codecs were mentioned. Quite tempting....I did not realize the Alphalink uses codecs and clocking is some kind of 'half as complicated' from the DIY point-of-view.
 
jdbakker said:
Svart said:
JDB, how would you feel about putting together a tiny MCU(or small FPGA)/DDS setup for clock generation?

Well...

I've thought about it on and off for some time. I would probably use one of those newer 1GHz SAW oscillators driving an AD9912 driving a bandpass filter with an AD951x clock distributor. Add a microcontroller, a cheap TCXO for an absolute frequency reference (the SAW has good phase noise when compared to the ref multiplier in the DDS, but not-so-great long term drift) and options for digital readout/control. Possibly add a few LVPECL->CMOS translator dongles so you can run a balanced clock to the converter(s) over twisted pair and only go single-ended at the chip's own ground reference. This offers milliHertz-level frequency tunability over a wide range indeed, will VariSpeed all you like, with jitter performance to rival the best canned fixed-frequency oscillators.

However, I don't need one myself, and this kind of tech complexity gets close to 'day job'-levels. Add the fact that you'd need two maybe three complex components in CSP/QFN and home-soldering is out, so someone (ie: me) would have to build and test them. Even at friends-and-family rates the module cost would be at or over $200 (and add up the cost of the major parts I've mentioned earlier and see how close you get...), and at that price I wouldn't blame anyone who pointed out that you can get an entire ADA8k-class converter for the same money.

Or am I being overly pessimistic?

JDB.
[yes, I know the boo-tique CD clock upgrades cost as much and offer way less performance]

;D

Not overly pessimistic.  BUT I used an 8051 to control a 9911 which used a 500mhz LVPECL clock source.  Remember me telling you about the SIlabs SI530 clock?  Thing of cheap beauty she is.  You can get them in 1ghz now too.  They only went up to 500mhz when I was designing one into my tuner.

8051(or Actel Igloo): <5$
AD9911: 20$
SI530: 15$

You could probably go for a DDS with less functionality to save some cash too.  These AD parts are EXTREMELY sensitive to their reference clocks, much more so than their datasheets would suggest.  Tweaking their loopfilters didn't help much either.  This was before finding the Silabs parts.

That setup has phase noise lower than my EXA can measure.


Yeah the alphalink uses a bunch of stereo codecs.  They spec the same as their high-end chips but are easier to use.  Sounds like a win-win to me.  SSL/Sydec didn't fool around with this design, it's damn fine in it's simplicity and elegance.  They use an FPGA to control it all.  Looks like the clocking and division are done by the FPGA too.  They have some XOs that trace right to the FPGA and the clock lines from the codecs trace to the FPGA too.  Strange, cause I always thought this was a HUGE NO-NO.  I suppose you could do it if you can ensure a clean output.  There is no telling what they stuck in that FPGA.

Oh they also use a nice fat open frame switcher in the box too, an off the shelf part.  Didn't recognize the brand though.  probably some OEM company.
 
Just a note: The AD9911 costs in Germany already 46Eur.
There is no doubt that you can make a design that outperforms many commercial designs but you have to put a lot of effort and money in it. If anyone wants to do that, feel free to do so.
Anyway I like the discusssion about the optimal wordclock implementation. I gives ideas for projects in the future. For now and a more easier to do design I think the CS2xxx family is a good choice, because you can use them without controlling it by a MC.

Raphael
 
rkn80 said:
I think the CS2xxx family is a good choice

I would strongly recommend against using those. Their practical jitter performance is on the order of a few hundred ps, which might be barely enough for consumer DVD players (their target market), but it will greatly compromise the performance of the converters you use.

JDB.
[rule of thumb: if it's an IC and it has an internal (VC) oscillator, it has too much jitter. There are some exceptions, but they are few and far between]
 
Hu,

datasheet states: CS2300 period jiter 35ps rms, 50ps rms base jitter, 150ps rms wideband jitter. That's better then many PLLs have.

Raphael
 
rkn80 said:
datasheet states: CS2300 period jiter 35ps rms, 50ps rms base jitter, 150ps rms wideband jitter.

Yes. And what you're looking for is <10ps jitter.

(Plus those are ideal-case figures; last time I measured I got rather higher numbers -- but Cirrus isn't unique in that regard)

rkn80 said:
That's better then many PLLs have.

Yes. And that's why you can't use a generic PLL here.

(A first-order estimate of jitter impact can be found here; Bruno Putzeys has published an AES paper that goes into (much) more detail).

JDB.
 
After carefully reading the last few replies I've a little bit the feeling that we're talking about different things. So I'ld like to clarify.
I'm still looking for a nice solution for the external wordclock sync. The solutions with the AD991x devices are fine for a VariSpeed design and I think I would definitly go for something like that for a VariSpeed design. There you can't avoid a microcontroller solution because you need to control the DDS somehow. But I don't see how to use these implementations to get a clock signal that is synchronous to an incoming wordclock signal because the AD991x devices expect a much higher clkin than a wordclock. And that's where I was thinking of let a CS2300 come in.

Raphael
 
rkn80 said:
I'm still looking for a nice solution for the external wordclock sync.
Yes, I get that.

rkn80 said:
The solutions with the AD991x devices are fine for a VariSpeed design and I think I would definitly go for something like that for a VariSpeed design. There you can't avoid a microcontroller solution because you need to control the DDS somehow. But I don't see how to use these implementations to get a clock signal that is synchronous to an incoming wordclock signal because the AD991x devices expect a much higher clkin than a wordclock.

You use a PLL.

As you probably know, a PLL essentially is a control loop around an oscillator, using a Phase Detector or Phase/Frequency Detector (PFD) and a Loop Filter to lock the oscillator's phase and frequency to (a multiple of) the reference input.

For us, the reference input is WC in (AES is possible too, but let's not muddy the picture), and the oscillator drives the converter's MCLK.

In the DDS scenario you feed both the DDS output and the WC input to the microcontroller. The microcontroller then implements a PFD, either in software or helped by one or two external D-flipflops. The microcontroller also runs a digital loop filter, and adjusts the phase and frequency of the DDS to match the incoming word clock.

In the VCXO scenario the VCXO gives you the converter's MCLK and (after a divider) an internal WC. If you want to lock to an external WC, you feed both the internal WC and the external WC to a PFD, the output of the PFD goes into a (possibly analog) loop filter which then drives the voltage-driven tuning input of the VCXO. If you have all the polarities and time constants right, this will lock the VCXO to the incoming word clock.

Or were you talking about something else?

(One big advantage of a PLL-in-software is that it is much simpler to implement a dynamically changing loop filter, so that you can have a wide bandwidth for fast capture changing into a narrow bandwidth for best phase noise. But maybe that's a bridge too far for a DIYable implementation).

JDB.
 
Svart said:
8051(or Actel Igloo): <5$
AD9911: 20$
SI530: 15$

...and about 20..30dB higher phase noise than the $50 SAW + $50 AD9912. (Did you test whether the Si530+AD9911 had better phase noise than a good 100MHz XO + the 9911's ref multiplier? Looking at the data sheets I expect it would be equal or worse).

Call me a perfectionist, but that 1GHz SAW oscillator gets awfully close to the performance of the Wenzel ref kit they used to spec the 9912, and that sounds mighty appealing. If we must solder LFCSPs I'd rather shell out some more bucks and do it just once with no nagging need to go upgrading later.

JDB.

 
JDB,

ok I see, we're talking about the same. Sorry. My fault. I had the impressions that the discussion tends more into a VariSpeed clocking then wordclock sync.
I'm still a little bit scared by a software PLL. While I would not have a problem with it because I've some programming devices for different controllers I suspect that this is to far beyond the means of many DIYers. I think the limit is something easy like a ATtiny because these devices can be easily programmed via PonyProg and a serial interface by almost everyone with a PC. So it might be ok to use such a device to control something via I2S. But for an accurate software PLL you might need a more sophisticated MC and very often you need special programming tools to  program them via a JTAG interface. Or do you think that the PFD can be implemnted on a ATmega?

Raphael
 
rkn80 said:
Or do you think that the PFD can be implemnted on a ATmega?

That's actually what I would use.

I'm unsure how to judge the programmability-barrier. I work with these devices on a daily basis, so I even have a USB-ISP programmer in my home lab. Cost me all of 30$ off eBay. If that's too much money, there's PonyProg (and a few like it), but does that require a 'real' serial port or are USB dongles supported as well?

JDB.
 
I agree with you that using a microcontroller makes it much easier to design because then you can do something like Apogge's Big Ben: Drive a DDS (like already suggested) and implement the PFD in the digital domain.
I'm quite unsure about the programming barrier, too. Like you I have to program devices like DSPs and microcontrollers for my job and I have the programming tools for the AVRs at home. So for me it would not be a problem doing so.
Another idea would be to offer pre-programmed chips for those who cannot flash a microcontroller themselve.
Anyway: I think you cannot feed the MCLK from the DDS directly into a ATmega but you could pick it up directly behind the divider network and compare the wordclocks.

Raphael
 
I spent this Sunday afternoon with reading about DDS chips. It's all nice as long as you don't think about how to build such a board yourself. I'm not really scared by SMD but a LFCSP package is definitly nothing to be soldered by everyone. While the pads could be done the inner big pad is more difficult because it has to be connected to the ground plane. The only idea I'ld have is to make a hole under the pad and put some tin-solder in it hoping not to produce shortening between the pads. (Of course there is the alternative of giving it to a company, but that makes only sense for bigger quantities, otherwise the price will become so high that you can already go and buy a commercial clocking device for your rack I think). So I think the risk is simply to high because the AD9911 and AD9912 cost a lot of money.
JDB did you already solder a LFCSP and if so ,how?

Raphael
 
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