I was looking at SONET / OC-3 type chips from SiLabs (DSPLL) and NSC LMK04000 series to slave to WC or internal (free run from DSPLL sample clock), but the data is not characterised for our audio purposes.. So it is frustrating to figure out response without spending the dosh on eval boards (and maybe renting some high end test gear to complement the lab here)... Have to use your imagination (or fantasize?) about the spurs for audio sample frequency multiples when bending the output frequencies to our purposes... Remember the A/D is a modulator that also modulates the power supply and jitter into the signal of interest...
And I remember of course the differences using the simulator for the NSC part does not support the low WC frequencies directly despite the datasheet saying it does (the simulator assumes a different mode of operation)
I haven't looked at it about a year, but the good news may be that on the DSPLL chips from SiLabs, jitter feedthrough for the DSPLL pins, XA and XB, (a.k.a the "DSP sample clock") input to the output is reduced below 12kHz... Might not be enough though; can't remember... Everything else is near 0dB perfect feedthrough.... Maybe the clock osc/xtal I was using only had some alleged spurs below 12k, so the combination of the response of the clock and the DSPLL chip worked out on paper....
I think Multigig had something that I was planning on maybe using to pre-clean or provide reduced DSPLL clock jitter... But it seems that they have assimilated into Micrel and I can't readily find the datasheet; most of Micrels native clock stuff is junk for our purposes...
In theory, with the simulator for NSC and the like I think I was getting near 0.8ps ~ 0.6ps of jitter... But I'm not sure I believe it.... In theory true 24-bit needs jitter somewhere near 0.4ps...
Of course, slew rate of differential clock swing can help in the additive jitter department.. but then distribution will have sharp edges and more RFI possibility and signal integrity analysis with termination would be critical... Keeping in mind that the IBIS models for signal integrity simulation are sometimes not accurate direct from the manufacturer...
I wonder what would happen if an uber sharp PECL (converted to single ended with appropriate loading on both of the diff lines) would do to performance of the TI ADC parts mentioned in this thread when impinged upon the CMOS clock input to said chips (after proper level conversion if needed)?
Rochey? thoughts? (over temperature too... would the clock section of some of the TI chips work better cold to reduce the Johnson noise perturbing the switching cross point?)
<dreaming mode>
It would be awesome if the ADC chips used true differential ECL (or better PECL) style of clock inputs and that their circuits were truly differentially clocked internally to the IC (but also able to be run single ended for consumer apps)... (hint...)
Only down side might be the need for more power supply and accoutrement near/into the chip (thicker bond wires? bond ribbon on the ol' wedge bonder?) to handle the fast and sharp current switching
but for consumer apps, running the proposed chip at a reduced clock swing spec might still be fine
...
</dreaming mode>