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rkn80 said:
It's all nice as long as you don't think about how to build such a board yourself.

I would agree.

I have soldered boards with LFCSPs (and QFN and the like), but I use a stainless steel stencil to apply solder paste and then reflow on a hot plate. Even then it's not hard to screw up.

For low jitter you want high DDS voltage/current output and high DDS output frequency (to get the highest slew rate), and a high DDS clock to have some distance to the spurs (see AN-823 for details). The DDSes that you'd want to use for this clocking application all come in LFCSPs, with the possible exception of the AD9910 (100-TQFP). Even so there are some reports that the greater lead inductance of that package negatively impacts its performance. And the clock divider/distribution chip (AD951x) is another LFCSP part.

I'd say that the most viable DIY solution would involve not a DDS but a (pair of) VCXO(s), with either a discrete or microcontroller-implemented PFD.

JDB.
[and I don't know of any cheap evaluation boards that could help here, either]
 
I'd say that the most viable DIY solution would involve not a DDS but a (pair of) VCXO(s), with either a discrete or microcontroller-implemented PFD.]I'd say that the most viable DIY solution would involve not a DDS but a (pair of) VCXO(s), with either a discrete or microcontroller-implemented PFD.
I second that. I guess there are not many if any people on this board willing to try mounting LFCSPs at home and reflow them on a hotplate, even if they tried that experimentally before. Especially if more than one of them have to be stuffed on the pcb.
I tried reflowing once and it worked with a household plate, but it was just one cheap component on the pcb and I needed a few trials until i was satisfied with the result.
 
JDB, while I don't remember the phase noise numbers from the DDS I do remember the phase noise numbers out of our PLL which is driven by the DDS.  The PLL arrangement didn't equal the phase noise of my Agilent sig-gen although, it was lower than most low phase noise oscillators available.  Looking at a Triquint SAW osc, the 100hz phase noise of the SAW is higher than our design by 15db while it's 1k and 10k numbers trump our design by 5db and 10db respectively and that's compared to the output of our PLL.  For our DDS, I'd say that the 100hz number is probably about 5dB lower than our PLL output while our 1k and 10k are probably at least 15-20db lower out of the DDS compared to the PLL output.  I know that our PLL dominates the phase noise at those points.

Of course you'll have to take this with a grain of salt because it's not apples/apples.  We did a LOT of work getting those numbers from our PLL(ADF4113).  Currently(no pun intended) we get -93,-93,-115 at 100, 1k, 10k respectively.  We are essentially at the limit of the 4113.

Also keep in mind we weren't looking at jitter per se either.

If I get a chance I'll throw the setup on the EXA and take a measurement.


Silabs makes a programmable part that is on par with the 530.  It takes I2C and it's essentially a canned PLL/VCO(like all of their parts).  I think it's the SI570 but I'm not sure.  Don't know what frequencies you need either but you'd likely not get anything lower than 10M from silabs.
 
Hm, I don't want to give up here. What about the following design: DDS: AD9954 puts out a master clock (depending on performance either 24.576MHz or a multiple of it). Clock signal feed into a clock divider getting the internal wordclock. The internal wordclock is sent together with the external wordclock into a phase detector made of two D-flipflops. The outputs of the D-Flipflops are connected to an ATmega88 which also controls the clear pins of the D-FFs. The ATmega talks to the DDS via SPI and regulates the output clock with respect to the values got from them phase detector. With this setup we have a system that is doable because the ATmega88 can be flashed without having high-priced programming tools.
The AD9954 comes in a TQFP48 package which can be soldered by hand. Looking at the spec'ed SFDR (=>responsible for jitter) the AD9954 should play in a similar league like the AD9910 but it is not so expensive like the other DDS (with features you don't need) in TQFP. I think it gives a good balance between performance, costs and difficulty. My second choice would be the AD9858 but this device costs 54Eur while the AD9954 costs 26Eur. That makes it more attractive for a DIY project I think. Of course if we have a working design we can always think of making a higher performing design using one of the expensive devices.
Where I'm quite unsure is the clock divider especially if we have higher clock rates then 24.576MHz. I'm not sure yet, wether I want to use a 'standard' synchronous counter (cmos logic) or a special divider like AD9515 (which comes again in a LFCSP).  I know that some counters can be really noisy...

Raphael
 
rkn80 said:
Looking at the spec'ed SFDR (=>responsible for jitter) the AD9954 should play in a similar league like the AD9910 but it is not so expensive like the other DDS (with features you don't need) in TQFP.

While it will function, the performance with the AD9954 is much worse than with the AD9912 or even the AD9910. This is partly because of the lower max clock frequency and partly because the 9954 is two generations older, and in the meantime much has been improved wrt spur performance. This is easier to see in the raw spur plots than in the SFDR numbers.

The ham radio community has done a lot of work in characterising DDSes lately, and while not all is directly applicable to audio clocking much of it offers interesting background. This is a good starting point.

Dividers are important, but a good squarer/limiter is at least as critical. The AD951x range offers both.

JDB.
 
How much worse would it be with respect to the jitter?
Btw. I think iClocks have a DDS with a main clock <200Mhz in it. I think I've seen that note somewhere on their homepage.

Raphael  
 
rkn80 said:
How much worse would it be with respect to the jitter?

Enough.

The main issue are the spurs. The ham radio folks using the older DDSes in Software Defined Radio have algorithms to re-tune the DDS a few kHz to minimize in-band spurs (and then undo that shift in software with DSP). This is not an option for us as we'd need continuously variable frequency output for Varispeed operation.

This is much less of a deal with the AD9912, as (for the same DDS output frequency) even without SpurKiller and cleaner DDS processes the interval between spurs is 2.5x larger, and spur magnitude 8-9dB down just because of the higher DAC update rate.

rkn80 said:
Btw. I think iClocks have a DDS with a main clock <200Mhz in it. I think I've seen that note somewhere on their homepage.

170MHz, I believe, but that's a completely different animal. First nobody in their right mind uses an iClock to directly drive a converter chip, and besides the only jitter spec I can find for them (1ps RMS, 6ps pp) is for the TCXO driving the DDS, not for the DDS output.

JDB.
 
jdbakker said:
170MHz, I believe, but that's a completely different animal. First nobody in their right mind uses an iClock to directly drive a converter chip, and besides the only jitter spec I can find for them (1ps RMS, 6ps pp) is for the TCXO driving the DDS, not for the DDS output.

Yes. Different animal. The reason why I was talking about it is, I'm wondering if we really need a 1GHz-device to generate a 24.57MHz clock synchronous to a word clock.

JDB, would you say that the already mentioned AD9910 is the best device if we want to go for a TQFP package (=> best compromise)?

Raphael
 
http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf

Seriously, check it out.  I2C programmable, 3x better stability than SAWs(according to the datasheet).  Programmable to any frequency from 10Mhz to 945Mhz.  You can get them in LVpecl, CMOS, LVDS and CML outputs too.

Don't know how much they cost but based on their other parts, probably a lot cheaper than the other ideas we've been discussing.
 
rkn80 said:
The reason why I was talking about it is, I'm wondering if we really need a 1GHz-device to generate a 24.57MHz clock synchronous to a word clock.

If all we wanted was a 24.576MHz refclock we could even do it with a 10MHz DDS and sufficient bandpass filtering (or injection locking).

rkn80 said:
JDB, would you say that the already mentioned AD9910 is the best device if we want to go for a TQFP package (=> best compromise)?

It looks like it. Other TQFP DDSes have higher current output at 1GSps, but the 9910 would appear to have best spur performance.

Svart said:
http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf

Seriously, check it out.  I2C programmable, 3x better stability than SAWs(according to the datasheet).  Programmable to any frequency from 10Mhz to 945Mhz.  You can get them in LVpecl, CMOS, LVDS and CML outputs too.

I know. I mentioned it here some time ago, and some of the radio amateurs are using it. However, stability isn't very important here (can always lock to an aux TCXO), and it can't do continuous variable slewing over more than +/-0.35% which is insufficient for Varispeed.

I've said it before and I'll say it again: it might be better at this stage to either (a) support Varispeed only through a traditional tunable LC oscillator + PLL (still better jitter than mid-market equipment) or (b) not support Varispeed at all. Even with a TQFP DDS you're probably looking at a 4-layer PCB and hairy routing to get the best performance.

JDB.
 
I was looking at SONET / OC-3 type chips from SiLabs (DSPLL) and NSC LMK04000 series to slave to WC or internal (free run from DSPLL sample clock), but the data is not characterised for our audio purposes.. So it is frustrating to figure out response without spending the dosh on eval boards (and maybe renting some high end test gear to complement the lab here)...  Have to use your imagination (or fantasize?) about the spurs for audio sample frequency multiples when bending the output frequencies to our purposes...  Remember the A/D is a modulator that also modulates the power supply and jitter into the signal of interest...

And I remember of course the differences using the simulator for the NSC part does not support the low WC frequencies directly despite the datasheet saying it does (the simulator assumes a different mode of operation)

I haven't looked at it about a year, but the good news may be that on the DSPLL chips from SiLabs, jitter feedthrough for the DSPLL pins, XA and XB, (a.k.a the "DSP sample clock") input to the output is reduced below 12kHz...  Might not be enough though; can't remember... Everything else is near 0dB perfect feedthrough.... Maybe the clock osc/xtal I was using only had some alleged spurs below 12k, so the combination of the response of the clock and the DSPLL chip worked out on paper....

I think Multigig had something that I was planning on maybe using to pre-clean or provide reduced DSPLL clock jitter...  But it seems that they have assimilated into Micrel and I can't readily find the datasheet; most of Micrels native clock stuff is junk for our purposes...

In theory, with the simulator for NSC and the like I think I was getting near 0.8ps ~ 0.6ps of jitter... But I'm not sure I believe it....  In theory true 24-bit needs jitter somewhere near 0.4ps...

Of course, slew rate of differential clock swing can help in the additive jitter department.. but then distribution will have sharp edges and more RFI possibility and signal integrity analysis with termination would be critical...  Keeping in mind that the IBIS models for signal integrity simulation are sometimes not accurate direct from the manufacturer...

I wonder what would happen if an uber sharp PECL (converted to single ended with appropriate loading on both of the diff lines) would do to performance of the TI ADC parts mentioned in this thread when impinged upon the CMOS clock input to said chips (after proper level conversion if needed)?  

Rochey?  thoughts?  (over temperature too... would the clock section of some of the TI chips work better cold to reduce the Johnson noise perturbing the switching cross point?)

<dreaming mode>
It would be awesome if the ADC chips used true differential ECL (or better PECL) style of clock inputs and that their circuits were truly differentially clocked internally to the IC (but also able to be run single ended for consumer apps)...  (hint...) ;)

Only down side might be the need for more power supply and accoutrement near/into the chip (thicker bond wires? bond ribbon on the ol' wedge bonder?) to handle the fast and sharp current switching :(  but for consumer apps, running the proposed chip at a reduced clock swing spec might still be fine :)...

</dreaming mode>
 
Twenty Log said:
I wonder what would happen if an uber sharp PECL (converted to single ended with appropriate loading on both of the diff lines) would do to performance of the TI ADC parts mentioned in this thread when impinged upon the CMOS clock input to said chips (after proper level conversion if needed)?

Meh. Given the residual jitter of even the best ~25MHz XOs (at room temperature!) ultrafast slewing doesn't help enough to be worth the effort. AC-coupling to the local switching threshold does help, or...

Twenty Log said:
It would be awesome if the ADC chips used true differential ECL (or better PECL) style of clock inputs and that their circuits were truly differentially clocked internally to the IC (but also able to be run single ended for consumer apps)...  (hint...) ;)

Yeah, that's been suggested but not likely to happen.

JD 'big customers don't care enough' B.
 
jdbakker said:
Twenty Log said:
It would be awesome if the ADC chips used true differential ECL (or better PECL) style of clock inputs and that their circuits were truly differentially clocked internally to the IC (but also able to be run single ended for consumer apps)...  (hint...) ;)

Yeah, that's been suggested but not likely to happen.

JD 'big customers don't care enough' B.

well, one promotion later, and I'm the one that decides what goes into new performance ADC/DAC's at my employers.

I don't see differential clocking coming any time soon I'm afraid. We're already fighting to keep pincounts down (cost of die, cost of bond wire, cost of package). Add to that, the fact that most consumer systems (even the high end AVR's) don't have differential clock sources that I know of, leaves me with little I can work with. In the language of MBA folk I keep meeting (i don't have one...) -- "There isn't enough value proposition".

That's not to say it's a closed book, but the argument "for" isn't as strong as the argument "against".

I'm always open to influence though. PM me with arguments. (and keep that side of the discussion off the forum... no need to fuel the competitions' brain cells...  ;))

EDIT: I'll also add, that I have been wrong/incorrect just as many times as I've been right/correct ;)

 
I hear ya Rochey... Had the same issues in R&D for 2GHz cellular handset power amps for the radio section; we had our own unique challenges for bond out and we used a Kapton lead frame bumped for BGA style.... The market was wrung out of profit margin....

But I must admit... The first transistor was not cost effective and did not have value proposition ;D (well kinda... it certainly was not practical at that time, but it was a glimmer of hope and not having to wait for the valves to warm up...  Better power supply etc...)

Replica-of-first-transistor.jpg


Wow! look at those non-inductive bond wires!  ;D  It's not even a matched pair! hehehe

The proposed differentially clocked ADC would have to be in a different market of course and different price point (but at reduced volume yadda yadda)...  And as time goes on it would be like that first transistor changing to what it is today...

Maybe a little weak, but it's all I got until my next coffee break...  Anyone else?
 
My needs are for 44.1 / 48 / 88.2 / 96
I do mostly live recording, and when you have 128 inputs going over 1000 feet of fiber from the converters, through a digital console to multiple 128 track recorders and generating mixes fed to other multiple trucks for live broadcast, while resolving to the master video, Word Clock in is required.
I have yet to encounter the need to pull up/down in the field
 
jdbakker said:
Meh. Given the residual jitter of even the best ~25MHz XOs (at room temperature!) ultrafast slewing doesn't help enough to be worth the effort. AC-coupling to the local switching threshold does help, or...
...

I think I was also finding the same after some exhaustive searching this but my A/D project has been on hold for almost a year whilst waiting for some custom silicon (it also had a nice app for the TI TAS3108), so I am drawing from memory at the moment... But I found different frequencies of TCXOs and VCXOs and simulated ~25MHz using some of the SONET clock chips to have slightly better jitter; except when too many clock dividers in the LMK for example were involved to get back down to 25MHz range- so it has to be almost native in the PLL rather than some multiple near the 2nd PLL in the LMK04000 dual PLL chipies....  But again simulation... haven't built it on the bench...  It was no Wenzel in the simulation of course...  I do have a sample of an OCXO but its performance is.. eh so-so... probably the Johnson noise or something close in on the carrier...

JD 'big customers don't care enough' B.

Group_Buy == big_customers ? diff_clock : single_ended;  // Oh well.. it was a nice thought while it lasted in my brain...

Then there is the old (mildly unrelated) trick of using 2 A/Ds to sample and get an additional 3dB of performance... http://www.cirrus.com/en/pubs/appNote/AN331REV1.pdf

 
JDB, can you explain what you think what is important for selecting devices? Otherwise it will become a thread where we suggest parts and you will always say "no, because..." ;)

Raphael
 
Excellent discussion. Please continue. You guys have some great ideas here. But in my opinion, yer getting a bit carried away. But please continue anyways. I am following this closely. Once Raphael (or anyone else) starts selling PCB's, I can modify and build to suit my needs. And, as you already know, clocking is a very deep topic (of which I only know the basics). One more comment from me..... Not that many dudes use vari-speed. Yes, I imagine it's cool. In our studio, we generate all the tracks and we mix all the tracks. We don't need to do any vari-speed business. We track at 96kHz. We mix and master at 96kHz. We down-sample and dither to Red Book CD. Boom. That's it. Again, this is just my opinion. Twenty Log... You appear to be a new member here. Where you at in New Hamshire? I'm down here in Massachusetts. Thanks, DANA.
 
rkn80 said:
JDB, can you explain what you think what is important for selecting devices?

For the DDS:
- low spurs and/or a way to eliminate spurs
- high DAC update rate
- high DAC output current
- easy/fast frequency updates
- clean reference multiplier, if necessary

For the limiter/squarer:
- low noise
- well-defined input impedance to properly terminate the post-DDS filter

For the divider:
- low noise
- low dynamic current (ie: minimal supply glitching when outputs change state)

The best chip for the job on the market right now is the AD9912, although the AD9910 is probably an acceptable candidate. As far as I've heard AD have a few DDSes just over the horizon (release later this year) that would be even more suitable (but again in LFCSP).

The major advantages of the AD951x squarer/dividers is that they're fast and clean, and they have easily programmable non-power-of-two dividers which makes the implementation of a post-DDS filter easier. Plus you can more easily run them at higher speeds (=lower jitter) than discrete logic.

If you were to put a gun to my head, I'd say take a 9910 into a 5 or 7-pole LC filter into either a discrete limiter or an LVPECL->TTL converter chip, into a synchronous divider like the 74LVC163. This should give you jitter performance within, say, 3dB of a VCXO.

Without a gun to my head I would still go for a microcontroller PFD plus two VCXOs, one for 44.1/88.2/176.4 operation and one for 48/96/192 operation; add an LC VFO for Varispeed if you must. Go for frequency autodetection if you want to be fancy or front panel selectors for 44.1/48/varispeed if you want to be foolproof.

JD 'easier to design, easier to build, better performance at fixed rates' B.
[plus people who only ever run 44.1 (or 48) could cheap out and only buy one VCXO]
 
Hey mateys... sorry if I got a little deeper into the sea of chips choices... just on the quest for better jitter and frequency agility without spurs (maybe, hard to tell with those chips without testing them physically)..

I haven't looked at the AD clock DDS site in a while as at the time, siLabs 5326 and NSC LMK04000 were looking better with what AD had... at that time.. SpurKillers look interesting on the AD9912!  Will have to play with it...

Thanks,
-chris
 

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