jdbakker said:Have any specific questions? I generally use the Xilinx stuff at work, and several of the Digilent eval boards are cheap and powerful enough.
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I'd suggest sticking to 100TX, as that is nearly universally compatible and 'light' enough to consider implementation on a fast (ARM) microcontroller instead of (/in addition to) an FPGA. Three dozen channels at 24/96 should be enough for a start, no?
JDB.
I'm looking for a FPGA core that is cheap, easy to obtain in the US and EU, is DIY solder-able (no funky BGA packaging), available as an eval/devel board with 100Mbit Ethernet in an arrangement that would be easy to copy to our interface board and has a high enough clock to push 32 bidirectional 96k/24-bit channels to Ethernet (though the reality of 100tx being able to handle this data transfer rate uncompressed is questionable). EDIT: and the eval board should have enough pins available to actually test bi-directional 24-ch i2s operation.
Possibly this one?
We had a discussion with rkn80 about how many channels it would be cool to push.. there was an idea of supporting up to almost 200.. that's hard even for gigabit to handle reliably as a developer from a next-door firm tells me they have a hard time getting 500mbits out of a gigabit chip. I'm happy to keep it 100tx, though that might limit people to 24ch in/out until the driver would get multihead.