My First Chip! PCM5102 112dB Stereo DAC

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2Vrms is a standard being insisted upon by our consumer customers. There's a Dolby spec from a few years ago suggesting that line outs have 2vrms full scale outputs.

Believe me, if we could avoid the charge pump and the greaterthan5v output we would have :)

PRR - I'll have words with our technical writers. Thanks for the feedback.

Best regards, Rochey
 
First of all congrats!
I haven't read the datasheet yet(just skimmed it very fast) and it seems like a nice solution that doesn't require a lot of external parts.

You mentioned listening test. What configuration your chip was working in? External clock or detected from spdif signal? What would be the best configuration quality-wise?

m.
 
Congratulations Rochey !!  I've posted on here before, I have always liked Texas product :O)


Frank B.
 
Ethan said:
C'mon.  Don't rain on the man's parade!  ;)

No rain intended... This a rare opportunity to lean on somebody inside the walls... I admit more than a little personal frustration from past encounters with engineering reps who expressed interest but never really listened to what was (IMO) valid input. I appreciate that the cost scale of chip designs, means they are targeting high production volume, so DIY or hobby interests are not likely to be very significant to their big picture, but we can still pretend. (FWIW, I did my share of booth duty over the years pretending to care about every customer's suggestions, so mea culpa).

I'm sure they didn't add the charge pump on a whim, and the +6dB of level output will be a difficult number for competitors to match.  Rolling the glue circuitry like turn on/off muting inside is the kind of stuff that can really add up in sharp pencil cost comparison, as circuit board real estate and individual component placements, cost more these days than the jelly bean parts that usually make up this glue circuitry. This just may be the new manufacturing math, but I was already dealing with sharp pencil bean counters where I used to work, while the dynamic has evolved further toward benefits of more integration.   

This also shifts some more of the design work load from the final implementation engineer upstream to the chip designer, a good thing from most customer's POV, if there isn't a painful per part cost premium.

JR
 
michal_k said:
First of all congrats!
I haven't read the datasheet yet(just skimmed it very fast) and it seems like a nice solution that doesn't require a lot of external parts.

You mentioned listening test. What configuration your chip was working in? External clock or detected from spdif signal? What would be the best configuration quality-wise?

m.

Michal,

We ran with an S/PDIF input to an SRC4392 (S/PDIF + Sample Rate Converter) but bypassed the SRC. Inputs were standard CD's, with the S/PDIF being split into 2 systems in many cases, ours, and the customers' current product, then AB'd.

We did tests with and without the PLL. Most customers preferred both to their current comparable product. There was a slight preference for nonPLL in some places, but most complimented us on how well the sound holds up in PLL mode.

In addition, we demo'd the low latency vs classic response interpolation filters... it seems everyone has a different opinion on which is best!

thanks for the feedback all!

/R
 
Awesome stuff! Congrats  :D :D

Must be really satisfying to be a part of such a development.

Cheers
 
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