generate bit clock from Word Clock input

heya folks

does anyone have a circuit for generating the bit clock from an external word clock source. If it's not obvious - i need to generate the bit clock for an ADC from an external wordclock (so that everything is synchronised)...

thanks guys...

R

mmmm
As far as I know this is not really easy to to do this (need a PLL?)...

what is it for?

Does anyone have a link to anywhere that describes the wordclock format?

A while back I worked at a studio that had a 2U rack display that showed the time when you fed a wordclock signal into it. I was thinking about the possibilities of programming a PIC to do this.

If the bit clock frequency is lower than WC then you might try a series of CD74ACT163 binary counters preset to the right divider and then decode the outputs with cascadable logic comparitors.

Joe

The bitclock is higher than the wordclock. The wordclock is fs*2 and the bitclock is often fs*256, but can also be fs*128, 384, 512 or even 64 in special cases.

Best regards,

Mikkel C. Simonsen

So you'll need a PLL with a divider of 32, 64, 192, or 256 in it's feedback loop, depending on chip type..

Jakob E.

The PLL filter setup and design (and the stability of the oscillator) will determine jitter of this clock. In radio, this was often called phase noise or PLL noise. If you're reading up on PLL's you might see it referred to as that. In radio, the timing isn't particularly critical (at least not in FM or AM) but the generation of noise is.

You might want to check - TI might have a part that will do what you need already?

Naa..

I really do not think that "internal" clocks has anything resembling jitter problems.

Jitter comes from transferring serial digital streams from one unit to the next, with the needed clock regeneration..

Read this thread for some very good information regarding this:

http://recforums.prosoundweb.com/index.php/t/2133/0

Jakob E.

Hang on I`m confusing myself here. The 2U display I was talking about displayed SMPTE code time, & thats what I was thinking about trying to get a PIC to display. Is this going to be wildly different to doing it with a wordclock i/p ?

I really don`t know much about the differences apart from the BNC 75ohm connections for wordclock. Any sites that give more detail on this ?

wordclock just aligns stuff... it doesnt contain any positioning info at all. SMPTE is special in that it contains the positional info.

The jitter does come from moving data from one unit to the next but that's what you are typically doing with wordclock plus AES, TDIF, SPDIF, or lightpipe. If the PLL is 'hunting' then it makes jitter in the regenerated bit clock signal. And getting a PLL to not hunt is a challenge and a half.

wow, thanks for the replies to the thread guys,

I kinda gathered that a PLL would be required, but I still have no idea of the kind of circuitry required.

TI has the PLL170x devices that'll take a 27MHz input (used for DVD's decoders etc) and generate the Fs*256 etc, but not synchronised to a wordclock (from what i can tell)...

DOH!

help

R