Calculating Attack & Release Times..... help, I give up:(

Hey guys, once again the lovely fleet of "professional" engineers here have left me hanging, so once again I come to the board for some real answers  ;D

I'm trying to better understand the math behind calculating attack & release times, it seems I'm overlooking something, as my time constant (t) calculations don't end up with the real world results.  The results are almost always at some multiple of (t), Am I missing something?  Or are the attack & release times a total approximation?  Way I understand it, changing attack time will actually alter release time as well, and vice-a-versa, because of R-C value interaction.  Specificially what I'm trying to do here is manipulate the attack and release times on the talkback compressor, though this would apply to anything really, and rather than just twiddle a pot to see what happens, I'd like to take a more scientific approach.

Below is a pic taken from the SSL comp (Set to 4:1 Ratio, 30mS Attack, 100mS Release).  Since Attack/Release times are known for the given Res/Cap values, figured it would be a good example to analyze.

As I understand it, Attack is calculated using parallel equivalent of R1 & R2 & R13 * C1.  So this would give me a result of 71K * 0.47uF = 33mS.  OK, that works out.

However, changing R1 to 82K for a 10mS Attack time would give me: 44K * .47uF = 20mS.  Is that right?  If not, then what am I missing?

Looking at release time (supposedly 100mS) of the attached pic, as I understand it R1 is not taken into equation since discharge path of C1 is through R2 & R13, so simple t equation would give me about 46mS, which is about 1/2t.  So once again, the math doesn't add up.

Thanks in advance for any help.

The simple RxC defines one time constant which will get you to roughly 63% of the terminal voltage =(1-e^(-t/RC)) . Three time constants will get you close enough for government work (95%).

I do not know of a standard convention wrt dynamics processors. Some probably look at the response to a tone burst on a scope and empirically look at the results. These results can vary depending on linearity or logarithmic accuracy of the side chain gain law. and even initial conditions.  Ratioing VCAs with good log convertors in side chain should be pretty good (dB law), other less consistent gain elements and side chains may deliver more variable results.

JR

How accurate do you need it to be?

As you say, R1 isn't part of the discharge path as the voltage stored at C1 will always be more negative than the quiescent voltage behind D9 and current will not flow back through D9. So, the value of R1 has no bearing on release time.

R13 is large enough to present a negligible load on C1 by comparison with R2, therefore R2*C1 pretty much determines your release time and R1*C1 determines the attack.

But, R2 in series with R1 form a voltage divider, so reducing R2 or increasing R1 will both slow the rate of charge AND increase the threshold by reducing the available voltage at C1. This is why attack, release and threshold inevitably always interact to some extent.

Your marked t values look wrong to me too. I may well be missing something!

The simplest way to "see" what's going on would be to do a transient sim of the circuit and pprobe the waveforms. So you can .step the RC time constant resistors and look at what effect they have in circuit.

The two resistors will be interactive, R2 will not only affect release time but also the peak value (it will load down the R1..).

To reiterate: one time constant is 63% reduction and we usually slam harder. But this must be multiplied by the VCA response curve, and the time-constant fudge-factor is open to interpretation (90%? 95%?).

> Way I understand it, changing attack time will actually alter release time as well

It is possible to separate the two. This needs a more complex circuit.

With the simple circuit, attack/release ratios as small as 30:100 or 1:3 are sure to interact. If we use your 270K:100K, the gain has fallen from near unity (for small attack large release) to 1:0.27, skewing your threshold.

It might be better to put the release resistor on the other side of the attack resistor, since release is typically longer/larger than attack.

I don't see "30mS" for 270K and 0.47uFd. Yes, with 270K||100K it is close, but 0.29 low-- it isn't faster, your bar is lower.

The purpose of R14-R20 D8 D10 is unclear to me.

I've told this story before but it's worth repeating. Years ago I was involved with selling a vinyl NR kit. This kit was based on the CBS developed CX NR system. CBS provided proforma schematics for licensees, detailed specifications, and even a copy of the encoder schematic (designed? and built by Urie).

Long story short, the encoder and decoder side chain circuit implementation was not symmetrical, and the decoder involved an interaction between the attack and release components being effectively in parallel. This caused a 10% error in attack time constant between the published spec and the actual encoder that were correct, and the CBS provided decoder circuit designs that were wrong.

I didn't used the published playback circuit as is, but made several improvements, including correcting the attack time to agree with the spec and encoder. I mentioned my discovery of the error to CBS and forgot about it. Literally weeks before my kit article published i ran into a Urie engineer at the AES show who was familiar with the CX program and he said "so you're the guy who found the mistake." Then he told me how CBS had them change the encoder to the wrong time constant because there were tens of thousands of decoder built and in the market that were wrong.. but CBS never told me.

Luckily I was able to make a frantic phone call to the magazine and correct my decoder to be wrong too, apparently the new right.

So even professionals who do this stuff for a living and should know better can get tangled up with such things.

JR

Note: when attack and release are specified as RC time "constants" there is not confusion about interpretation, it is the simple RC product, however "attack time" or "release time" is not as simply interpreted. 

The most commonly accepted definition of attack time amongst dynamics designers is the time it takes to reach 90% of the steady-state GR; let's say you hit the compressor 10dB above threshold, with infinite to 1 ratio, the steady-state GR is 10dB; the attack time is the time it takes to reach 9dB GR. If the ratio was 2:1, steady-state GR would be 5dB; attack time would be the time to reach 4.5dB GR.
Release time would be similar with the compressor submitted to the same 10dB above, and the signal being suddenly dropped down just below threshold.
Now, some designers would say 12dB, some would say less.
Anyway, that's trying to describe the Joconde by defining two pixels. There's an infinity of curves passing through two points (linear, expo, log, and many others).
dbx made it clear right at the beginning, by labelling their attack and release controls in dB per time unit, but even that is not cast in stone, because the rate is not constant, depending on how much the signal is over threshold in a dbx-type RMS detector.
With the simpler type of "peak" detector using cleary defined time-constants (in the math sense), the relation between the input signal and the detector's output is easily predictable, but still the response law of the VCA element will alter the final GR vs. time transfer.

Guys, thanks.  Have a slew of questions and responses now though, as I'm still totally unclear here how to proceed.

Basically, if I'm interpreting your responses correctly, basically the listed attack/release times with such circuit are a real ballpark estimate, and what might be called out as 30mS Attack and 100mS release on the front panel, really isn't necessarily 30mS attack and 100mS release. 

Seems maybe spice and or just prototyping and taking actual measurements will be the only way to really get any kind of accurate measurement, and even then with a simple R-C circuit like above, actual times will vary greatly depending on settings, due to value interaction.

Some questions/responses to some things:

MagnetoSound said:

So, the value of R1 has no bearing on release time.

Click to expand...

Agreed

MagnetoSound said:

R13 is large enough to present a negligible load on C1 by comparison with R2, therefore R2*C1 pretty much determines your release time

Click to expand...

[/quote]

Agreed

For sake of this discussion, R13 can be ignored.  Impact on parallel resistance with R2 is negligable.  So 100,000 * .00000047 = .047S, or 47mS.  Hence my confusion, but I think PRR explained why this is above, simply due to value interaction with such low values.

MagnetoSound said:

and R1*C1 determines the attack.

Click to expand...

Disagree on this one (Though obviously I could be wrong).  As I understand, parallel resistance of R1+R2 * C2 would indicate attack.  Parallel resistance of 270K and 100K = approx 72K.  So 72,000 * .00000047 = .033S, or 33mS.

PRR - is this why you indicated moving the release resistor BEFORE the attack resistor?  In this new configuration, now attack would simply be R1*C1, and release resistor would now not have an affect on attack time.

PRR said:

It is possible to separate the two. This needs a more complex circuit.

Click to expand...

I'm all ears  ;D  Any examples you can point me to for reference?

PRR said:

It might be better to put the release resistor on the other side of the attack resistor, since release is typically longer/larger than attack.

Click to expand...

Please see my previous post - is my assumption correct?

PRR said:

I don't see "30mS" for 270K and 0.47uFd. Yes, with 270K||100K it is close, but 0.29 low-- it isn't faster, your bar is lower.

Click to expand...

Confused on this one, what do you mean by 0.29 low?

PRR said:

The purpose of R14-R20 D8 D10 is unclear to me.

Click to expand...

This is right off the original buss comp.  R14/R15 Set The Ratio (4:1 shown).  R17 & R18 are present in all ratio switch settings pulling on the opamp output, though I admit in all the many hours I have fiddled with this circuit I still don't quite understand why, other than it they are needed for it to work.  From what I can tell, R19 & R20 aren't really doing anything in this configuration, leftover remnants from 2:1 ratio position.

R16 sets the threshold

sorry if this is confusing.

90% of side chain voltage change is reached after 2.3 RC time constants. While your actual output gain change may depend on gain element law.

Attack time constant is as you described. All three R's in parallel while terminal voltage is to voltage divider formed by the two R's in series. Release time constant is the two R's to ground in parallel.

JR

JohnRoberts said:

sorry if this is confusing.

90% of side chain voltage change is reached after 2.3 RC time constants.

Click to expand...

John, thanks.  It's all starting to click.  Abbey's earlier comment regarding the 90% charge didn't fully compute until your post, so now knowing the 2.3 time constant multiple (which was the key piece of missing info in my calculations) all the math is now adding up (for release anyways).  So now (for 100mS release) I get 100,000*.00000047*2.3=108mS (obviously close enough).  I get accurate results within 5-10% for all of the other release settings.

As far as attack, I'm still a little fuzzy.  Simply multiplying by a factor of 2.3 actually puts me in the wrong direction.  I'm assuming because of the voltage divider being formed there's more to it (which is not the case for release).  I did see a pattern though for all of the attack time values, simply multiplying the input resistor (R1) times the cap (C1) and dividing by 4 gets me the indicated attack time for every switch position, so I can't help but think that's not a coincidence.

For example:

(30mS) - (270,000*.00000047)/4 = 32mS
(10mS) - (82,000*.00000047)/4 = 9.6mS
(3mS) - (27,000*.00000047)/4 = 3.2mS

I guess it's time to throw a wrench in the gear and bring up what I'm actually trying to manipulate, as it gets more complicated than the previous example as there's no parallel resistor to the capacitor.  I want to add one (if it is possible), so I can adjust release time as per the previous schematic, however not sure if this might cause any issues.  But even if I can, obviously I need to figure out what the current release time is so I can resize the cap value accordingly once a resistor is placed in parallel. 

Since there is no direct discharge path for the cap other than the gate of the FET, I'm assuming the existing values probably result in a very long release time.

Attack time seems simple, R*C gives me 10mS, although because of the issues above I don't know if I can rely on this as an accurate number.

I have this entire circuit modeled in ltspice, if memory serves correct I do get somewhere around 10mS attack for the 1K input resistor with this circuit.  However (with my current level of spice knowlege), I have no idea how to model release time, as to do so I would need to change the input voltage level to put it above threshold and continue recording data, so that I could measure the time difference.  If I could figure out how to do that, this might be much easier.  Anyone know?

Thanks.

You are giving this time constant stuff far too much though... with too many decimal places. Circuits like this are why they invented trim pots.  8) Do what sounds good.

Veering off on a different tangent after seeing that circuit, there is an nice trick to reduce side chain control voltage from getting into the audio.

Your C87- R84 network to add -6dB of the JFET drain AC voltage back into the gate to reduce distortion works, but doing it passively means CV changes will also be fed upstream into the audio signal path.  Since that same voltage node (FET drain) is connected to the opamp + input and amplified by the gain stage, we can predict that the output of opamp U205A will be exactly 11x that FET drain voltage. So we can recreate a buffered version of that drain voltage by dividing down that opamp by 1/11th (like with say another 10k and 1k resistors). Connecting C87-R84 to this buffered version of the drain voltage will deliver the desired distortion reduction, without driving control voltage artifacts into the audio path. Note: you could actually accomplish this using less parts (without the pad)  but it would take a high megohm resistor value that isn't common.

I see other things I would do differently, but not a big deal... but please consider my suggestion to get the control voltage changes out of the audio...

JR

Note: The VC feedthrough I am talking about is already attenuated 40 dB (2M/22k), so after the 11x gain down 20 dB or so, assuming the input is driven from a low Z, but it can be designed out completely for the cost of adding two resistors.

How about that? Should save you a little money and board space if it works.

Edit: removed faulty schematic

Yup that's along the lines of what I was thinking for less parts, but the ratio you used are presenting 100% of the AC voltage at the gate, we want 50% for minimum distortion. So if the opamp gain is 11x we want to divide by 1/22 so push the 1M up to 2M or drop the 100k to 50k, but 50k is not a 5% value. 

Note my 1/11th divider was before the additional 1/2 divide so 1/22 overall. 

JR

You're right, fixed.

Cretits where it's due, I remembered where I actually saw this config:
http://sound.westhost.com/project67.htm

.. and of yourse to JR (with infallible math..).

ruckus328 said:

Since there is no direct discharge path for the cap other than the gate of the FET, I'm assuming the existing values probably result in a very long release time.

Click to expand...

Pls note that the discharge path is via R86 & R55; in fact quite a fast release (signal-dependant too)!

tv said:

Cretits where it's due, I remembered where I actually saw this config:
http://sound.westhost.com/project67.htm

.. and of yourse to JR (with infallible math..).

Click to expand...

There are probably numerous variants of this. When I said it was a "nice trick", I was implying that it was a technique know to those skilled in the art and familiar with JFET and opamp designs.

The first example of this I recall seeing was in a sine wave oscillator loop gain stability circuit designed by Robert Cordell for the THD analyzer test set he published in Audio magazine a few decades ago. His application was slightly different as he had the JFET from the - input to ground to make variable gain instead of of attenuation, but it uses the same principle to buffer the drain node by using an opamp's NF relationships.  (I don't know if he copied it from somebody else, but he was (is?)  a pretty innovative circuit designer. )

I don't footnote every circuit idea I suggest that is in the public domain, but I have been a student of other people's designs for decades. That's how I learned much of what I know. I will sometimes identify things I think are novel but even there we must be careful. The ancients are always stealing our ideas. That's why we do patent searches, etc. If I consider something novel and my personal creation I will generally say so, but I don't publish my best work since getting out of the kit business, where that was part of the transaction.

JR 

PS My math is not infallible, just better than yours this one time.

err.. my math was on vacation, haha.. on a lazy saturday

Yup, sometimes I wish I could give answers without any numbers at all...  8)

JR