Matador
I dropped R17 so I now have 23.5 volts at the zener (i can't get it exactly to 24v as I don't have a large range of resistors). doesn't the voltage at R12 depend on the R11 value? I mean as soon as I adjust R11 to bias the fet then R12 just tracks this voltage from the fet drain. so I don't understand how I can get R12 to produce 21v if I'm going to then adjust R11 to bring the fet drain (and therefore R12) back to 10.5v.?
I'm clearly no expert when it comes to electronics but it seems for such a simple small circuit this is proving to be very difficult!
The entire string of voltages depends on the Q point of the JFET.
Perhaps this is best explained by looking at the load line for this circuit (stolen from my other thread):

The default load line is in red, and the U87A intended bias point is the blue square on that load line (at about 10V on the drain). Note that the slope of the load line is set by the drain and source resistors (and NOT the FET!).
But this plot assumes a nominal JFET: the actual V
GS that results in 10V at the drain (with 0.25mA ID
S) varies quite a bit from device to device. One can imagine that if you deleted all of the green lines the load line would not change, however the individual green line (representing the gate-source bias that intersects the blue box) would change from device to device. This is what setting R11 does: matches the bias so that the individual JFET idles at the design point.
However the implicit assumption here is that the U87 biasing string depends on the Zener keeping it's node at 24V! It could be the original JFET's didn't pull much current. However a modern 2N3819 can range anywhere from 2mA ID
SS all the way up to 20mA! That is a tremendous range for a single topology to cope with!
If you set R11 to maximum, then the drain voltage should be at maximum (the blue box is far to the right). As you lower R11, the blue box will move along the red line to the left, and drain voltage should decrease as the idle current increases. As R11 approaches zero the JFET will pinch-off and then the drain voltage will rapidly rise back up.
If you don't see this, then something else isn't correct in the wiring.
If you happen to have devices that have very high ID
SS, then you won't be able to make R11 large enough with a 10K pot to move the idle current down into the intended range, because the device will be pulling too much current and dropping all of your voltage across R17! If you take my plot, and move the top-most line (VGS=0V) up to 20mA (on my plot, it's about 12mA), you'll see that in order to drop the current back down to 0.25mA you'll need perhaps 4V gate-to-source bias, which would be 4V/0.25mA = 16Kohm!
Do you have perhaps a 25K pot to put in place? Or you could also add a 10K resistor in series with the pot of you can perform the gymnastics on the board with your soldering iron. I would also test 10 JFET's for ID
SS and pick one that's on the lower end of the spectrum.
Hope that makes sense.