John Linsley Hood/JLH unity gain buffer - comments and suggestions please

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steveh

Member
Joined
Nov 18, 2010
Messages
15
I'm interested in using the JLH output stage in a unity gain buffer as shown in the attachment.  In simulation, the circuit oscillates when fed a square wave if C4 is not present.  With C4, it only overshoots/rings before settling, although the ringing looks nasty as shown in the next post.

Is there a better way to compensate this circuit?  Any other general comments also welcome.
 

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What an ordeal. I bet you guys don't get much spam on this forum...

Ringing with 20nF load under 1Vp-p 20kHz square wave is attached.
 

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.asc attached.  I think I'm using only transistor models that come with LTspice so the results should be reproducible.

Will input filtering help with stability?  I want to make sure that the feedback loop is stable before/without using a filter.
 

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Try this. Try to optimize the snubber value to your real-circuit components - I doubt you will use 2n3904 as output devices..

With 10 Ohm buildout resistor added, the oscillation problem almost vanishes ...
 

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Waveform (from the posted schematic)
 

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It doesn't have voltage gain, or overall negative feedback to stabilize.

Any transient artifacts seem related to cap coupling between the base of the output follower and input to the current mirror.

If needed I would consider breaking up C4 into two caps. One from the upper node to ground and perhaps a second from the lower node to ground or negative supply.

Not sure what the rationale for this exercise is, perhaps a first order cancellation of changing Vbe drop with current to reduce distortion of a simple follower?  It seems the output load needs to be factored into this calculus (what is 47k and 200pf, some hypothetical typical load.).

Enjoy..

JR
 
Which JLH design is this? The classic power stage looks rather different:
http://electronics-diy.com/schematics/484/jlhnotesfig1.gif
http://www.tcaas.btinternet.co.uk/index-1.htm
 
rocket512 said:
Which JLH design is this? The classic power stage looks rather different:
http://electronics-diy.com/schematics/484/jlhnotesfig1.gif
http://www.tcaas.btinternet.co.uk/index-1.htm

Based on the JLH, but with Q3 reversed to force unity gain.  I'm not aware of Linsley Hood using it himself.
 
Q3 Q1 form a HIGH-gain amplifier.

Yet Q3 Q2 appear to force unity-gain.

For very small signals, Q2 emitter shorts-out the signal current from Q2, reducing gain to very nearly unity.

The "spike" is only 50mV. This suggests that Q2 is being slammed to cutoff or high current (50mV across a junction is about 6:1 change of current; NOT "class A").

With Q3 and Q1 as similar devices and not-too-different currents, it is a 2-pole response tending to 180 deg phase shift. Assuming "any" further phase shift, plus Murphy, it's begging to oscillate.

C4 slows the loop, by slugging Q3 Emitter to Collector, and gets toward 1-pole response, but it is surely a lash-up and probably throws-away a ton of available response.
 
PRR said:
Q3 Q1 form a HIGH-gain amplifier.
.....

With feedback path across Q2 BE junction, and this forces it to approx. unity gain.

How come that nobody mentioned nasty current spikes that occur in the output transistor chain? This is inherent to the "JLH-esque" circuits topology and can't be avoided. The only remedy is to band-limit the input, so that the "wave-fronts" are tappered and beveled to begin with. And snub the inverter transistor so that it "behaves" at transients, so that output pair doesn't get slammed with signals that are going to confuse them.
 

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tv said:
How come that nobody mentioned nasty current spikes that occur in the output transistor chain? This is inherent to the "JLH-esque" circuits topology
Is it really? It looks to me as the normal behaviour of any amplifier topology. The current spikes created by applying a square-wave to a capacitive load reflect in all the preceding stages, even in the input current. Ther is some improvement to be made by adjusting the operating point of the output Q's. With the chosen input signal, they go into cut-off. Increasing the quiescent current by reducing R1 & 2 down to 1k seems to solve the problem.
The only remedy is to band-limit the input, so that the "wave-fronts" are tappered and beveled to begin with.
Right. That's why I previously suggested some 1st-order passive filtering. Assessing the stability of a circuit by slamming a square-wave doesn't look to me as the most rational way; looking at the Bode plot is much more informative IMO.
And snub the inverter transistor so that it "behaves" at transients, so that output pair doesn't get slammed with signals that are going to confuse them.
I'm not sure I understand what you mean by confusing signals...
 
abbey road d enfer said:
Assessing the stability of a circuit by slamming a square-wave doesn't look to me as the most rational way; looking at the Bode plot is much more informative IMO.

That's what I wanted to do as well, but couldn't figure out how.  Not shown on the schematic is the loopgain2 probe which I deleted after being unable to get results that made sense to me.  I also can't see how to disable the feedback to simulate open-loop behaviour without thoroughly changing how the circuit works.

Is a .ac plot of V(out)/Ie(Q3) meaningful?  If yes, what value corresponds to unity loop gain?
 
steveh said:
abbey road d enfer said:
Assessing the stability of a circuit by slamming a square-wave doesn't look to me as the most rational way; looking at the Bode plot is much more informative IMO.

That's what I wanted to do as well, but couldn't figure it how.  Not shown on the schematic is the loopgain2 probe which I deleted after being unable to get results that made sense to me.  I also can't see how to disable the feedback to simulate open-loop behaviour without thoroughly changing how the circuit works.

Is a .ac plot of V(out)/Ie(Q3) meaningful?  If yes, what value corresponds to unity loop gain?
I must admit it is not easy to assess the open-loop gain. I've tried to isolate the high-gain part from the voltage-follower but there's so much interaction between both that it doesn't give any significant result.
But just the standard Bode plot is fine. Without the resistor in series with C4, you see a large hump at 6MHz. Putting a 200r in series with it seems to reduce this hump sufficiently to make the circuit stable. I noticed the peak current clipping is not symmetrical, increasing the bias voltage to 15V helps.
 
I think you'd be much better off using a diamond buffer. The JLH circuit was designed before they had good complementary pairs.
 

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Or Allison buffer, or JLH's FET/BJT buffer, or pair of n-JFETs.  Lots of options, but I was interested in this one.

A late thanks for all the responses; I had more pressing issues to attend to last week.

 
To use a "JLH" stage, you must "want" to use it - because it has a "vibe of it's own" - as well as some quirks (I mentioned some before).

OTOH, you must spend some time with it, to find it's "sweet spot", where it will be very "musical" - unlike f.e. a diamond buffer, which is going to sound "uninspired" in comparrison.

You can also experiment with mosfets in JLH (if you're into such stuff), but with these the "current spikes" can be even more pronounced because of larger mosfet gate capacitances that can cause unwanted behaviour on transients and square waves.

Search diyaudio forums, lots of JLH-related builds and analysis there.
 
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