Clock Divider with 4:1 Duty Cycle

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Samuel Groner

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Joined
Aug 19, 2004
Messages
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Location
Zürich, Switzerland
Hi,

For a stand-alone (no CPU/uP) serial data transfer I need a clock divider with a 4:1 duty cycle. The clock is 16 MHz; the high output of the divider should last 64 cycles (or preferably as low as 53 cycles, but I presume 64 is simpler to derive), and the low output 16 cycles. I'd have taken two 8 bit counters (74HC590) which reset each other. Is there a smarter path?

Thanks for your help,
Samuel
 
Samuel Groner said:
For a stand-alone (no CPU/uP) serial data transfer I need a clock divider with a 4:1 duty cycle. The clock is 16 MHz; the high output of the divider should last 64 cycles (or preferably as low as 53 cycles, but I presume 64 is simpler to derive), and the low output 16 cycles. I'd have taken two 8 bit counters (74HC590) which reset each other. Is there a smarter path?

You can do this with a single 'HC590, a NAND gate and an inverter. Connect the inverter to QF (/64), this produces your output. Connect QD (/16) and QF (/64) to the NAND gate, and connect the output of the NAND gate to /CCLR.

(The output register on the '590 will make your off-time one cycle longer than intended with this scheme. Use a different counter ('HC4020), or a wider NAND-gate. Any async counter will give a slightly longer off-time due to its non-zero reset time. Textbook method would be to use a synchronous counter, and to have an additional register on the output.)

Samuel Groner said:
(no CPU/uP)

The simplest, most flexible and probably cheapest solution (cheaper than a CPLD, not much more expensive than bare logic) would be to use a microcontroller:

Code:
    turn output on (1 cycle)
    do nothing for 52...63 cycles
    turn output off (1 cycle)
    do nothing for 12 cycles
    jump to beginning (3 cycles)

If you're extremely concerned about jitter, you could reclock the output with a simple flip-flop.

JDB.
[what are your jitter specs? How tight does the 4:1 have to be?]
 
Thanks for your input! Here's what I've sketched with a '4020 (the 16 cycles low need to be exact):

divider_r1.gif


The reset input is active high (not active low as for the '590), so I've added an inverter.

I'm not sure if I truly understand how this should work; let's say we start with all counter outputs at low. This means OUT is high, and MR is low. After 64 cycles both Q3 and Q5 are high. OUT is low as it should. MR is high, thus all counter outputs are reset to low and OUT immediately turns high again, without waiting 16 cycles. What am I missing?

Jitter is not critical, anything less than a few nSpp should do. I'm looking for a solution without software programming, thus no uP.

Thanks,
Samuel
 
Samuel Groner said:
I'm not sure if I truly understand how this should work; let's say we start with all counter outputs at low. This means OUT is high, and MR is low.

Yes.

Samuel Groner said:
After 64 cycles both Q3 and Q5 are high.

No.

The first 64 cycles starting with a reset, Q5 is low, making OUT high.

On the 65th cycle (after the 64th clock edge following reset), Q5 goes high, making OUT low.

It takes 16 more cycles for the first occurrence of Q5 and Q3 high, resetting the counter, restarting the sequence.

Again: it takes a non-zero amount of time for the RESET to propagate through the gates and the counter; call it two or three dozen ns for this schematic with HC-logic. Your out-HI will be shorter by this propagation time, your out-LO will be longer by the same amount of time. Propagation time will vary with chip sample, supply voltage and temperature, but will be fairly constant if those parameters don't change, causing wander rather than jitter. If this is not acceptable then add a D-flipflop in the OUT-line, clocked by IN.

Hope this helps,

JDB.
[the 'lumped' representation of the 'HC00 makes my head hurt a bit]
 
OK, got it! I was first thinking of the counter outputs as just "divide by n" outputs, but that's of course not what they are as this would not make a counter. Thanks for your help!

The low-to-high transition delay is not critical, but the high-to-low relative to the next rising edge of the clock input is, as there is a lower limit (of 65 nS) by the set-up time of the serial data output. I see that this is getting a bit awkward as I need another signal where the high-to-low transition is advanced. I'll first have to draw a better timing diagram...

Samuel
 
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