Twenty Log

perfect sample/hold
« on: August 18, 2012, 08:53:12 PM »
quick query... if an A/D were preceded with a "perfect" ideal sample/hold with "perfect" jitter (aperture jitter and the like), theoretical/ideal droop characteristics, small hold noise, low feed-through, et cetera...

perhaps with a skewed S/H clock to allow the A/D chip, time to charge its switched capacitor inputs....

what would happen to the the specs ?  which specs would be affected by this theoretical beastie ?


JohnRoberts

Re: perfect sample/hold
« Reply #1 on: August 18, 2012, 10:42:56 PM »
I am not sure I completely understand the question but modern A/D convertors oversample at many times the nominal sample rate so the S/H is operating at very short aperture and hold times. The general error sources related to S/H diminish as sampling rate increases since the voltage delta between samples for even high slew rate signals is reduced to small amounts and hold errors are time related. 

I am not aware of S/H being a critical limitation in modern conversion accuracy while I am not an expert, i just pretend to be one on the WWW.

JR
Don't only half-ass tune your drums. Visit https://circularscience.com to hear what properly "cleared" drums sound like.

Twenty Log

Re: perfect sample/hold
« Reply #2 on: August 19, 2012, 01:10:16 AM »
Cheers. No worries. The theory/hypothesis looking to be exploited here is a jitter brain dropping. The thought is that there is jitter in modern IC A/Ds due to logic threshold variability in the internal clock circuitry within the IC... 

What if a more robust external S/H could provide the signal of interest as a pre-sampled stepped "DC" (with enough drive current and other "perfect" parameters) to the input of the A/D chip, where the stepped DC had step "tread" lengths in alignment with the sample rate (e.g., 5.6 MHz ~24MHz worth of tread length, skewed of course to allow "setup" times for the IC A/D etc.).

 if the external S/H had a more robust logic threshold certainty, could it improve jitter specs down stream (the A/D chip could sample at any time within its jitter-ry window and just be sampling a DC stepped voltage of which it was going to do/convert to anyway in its switched cap front end)

The difference here is that the external S/H has a more certain sampling paradigm (less "jitter")...
My reading of some analog devices datasheets tells me that this is nothing new but the difference is that this is indeed oversampling and audio bit depths as opposed to the original notions put forth by said older datasheets/app notes for lower bit industrial apps.   


 

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