Twenty Log
Well-known member
quick query... if an A/D were preceded with a "perfect" ideal sample/hold with "perfect" jitter (aperture jitter and the like), theoretical/ideal droop characteristics, small hold noise, low feed-through, et cetera...
perhaps with a skewed S/H clock to allow the A/D chip, time to charge its switched capacitor inputs....
what would happen to the the specs ? which specs would be affected by this theoretical beastie ?
perhaps with a skewed S/H clock to allow the A/D chip, time to charge its switched capacitor inputs....
what would happen to the the specs ? which specs would be affected by this theoretical beastie ?