old-days delay

hello everyone
I'm trying to get a digital delay out of old chips and logic ICs.. Someone here will say: stop! you don't need to, there are plenty of modern alternatives. Sure, but my purpose is to learn, I don't need a digital delay, I have many of them.

So here I have a schematic of a '80s digital delay
http://www.ed-sounds.com/board2.png

this is only the digital section: the input and output signals are filtered elsewhere with Emphasis and LPFs. Of course the feedback path and the mixing sections is done in analogue like every delay like this one.
The CPU that handles pots and switches is missing too..the only piece of CPU that is connected to this schematic is the 10-bit bus that supplies 4519 ICs on the center-bottom of the schematic, and another bit "PC0" that is responsible of the WE signal for the DRAM.
Last, there's a VCO input that accepts either a square wave or a triangle wave (with slighly rounded bottom), swinging from 2V(min) to 4V(max), with a maximum frequency of 16hZ.


So far what I understood is:
since the max delay is 1024ms, I think that the 10-bit bus from the CPU sets the ms time (2^10 = 1024), that all that logic under the DRAMs converts that number into address for the DRAM.
The ADC is a SAR+DAC, 12bit, and every bit is stored in 64k DRAM chip.
The VCO sets the sample rate for the conversion (acting on the Sample-Hold gates), but I don't understand what it happens when the VCO gets higher (or lower), how can the delay produce a modulation effect?
Furthermore looks like, after the S-H on the input, there's an attenuator that is engaged if the signal gets too hot, if yes, that condition gets stored in a 13th bit, and the attenuation gets boosted on the output.

It isn't clear to me how the address logic circuitry and the VCO circuitry are working togheter..and why is needed all that circuitry to set the address for the DRAMs..
can anyone help me understand?
many thanks
Dimitri

Dimitree said:

hello everyone
I'm trying to get a digital delay out of old chips and logic ICs.. Someone here will say: stop! you don't need to, there are plenty of modern alternatives. Sure, but my purpose is to learn, I don't need a digital delay, I have many of them.

So here I have a schematic of a '80s digital delay
http://www.ed-sounds.com/board2.png

this is only the digital section: the input and output signals are filtered elsewhere with Emphasis and LPFs. Of course the feedback path and the mixing sections is done in analogue like every delay like this one.
The CPU that handles pots and switches is missing too..the only piece of CPU that is connected to this schematic is the 10-bit bus that supplies 4519 ICs on the center-bottom of the schematic, and another bit "PC0" that is responsible of the WE signal for the DRAM.
Last, there's a VCO input that accepts either a square wave or a triangle wave (with slighly rounded bottom), swinging from 2V(min) to 4V(max), with a maximum frequency of 16hZ.


So far what I understood is:
since the max delay is 1024ms, I think that the 10-bit bus from the CPU sets the ms time (2^10 = 1024), that all that logic under the DRAMs converts that number into address for the DRAM.
The ADC is a SAR+DAC, 12bit, and every bit is stored in 64k DRAM chip.

Click to expand...

Yup, 12b +1 successive approximation.

I only see 8 address bits per memory chip so looks like 256x1

The VCO sets the sample rate for the conversion (acting on the Sample-Hold gates), but I don't understand what it happens when the VCO gets higher (or lower), how can the delay produce a modulation effect?

Click to expand...

Delay is the product of the number of clock cycles it takes for data to step through the memory, times the period of the clock. So 10kHz clock time 256 steps =2.5 mSec.

Furthermore looks like, after the S-H on the input, there's an attenuator that is engaged if the signal gets too hot, if yes, that condition gets stored in a 13th bit, and the attenuation gets boosted on the output.

Click to expand...

gain scaling from over range bit.

It isn't clear to me how the address logic circuitry and the VCO circuitry are working togheter..and why is needed all that circuitry to set the address for the DRAMs..
can anyone help me understand?
many thanks
Dimitri

Click to expand...

If delay is variable. small variation from changing clock frequency, large delay variation from changing address loop length.

JR

Dimitree said:

....why is needed all that circuitry to set the address for the DRAMs..
can anyone help me understand?
many thanks
Dimitri

Click to expand...

DRAMs are multiplexed - there may only be 8 address lines but by the magic of the 157 2-1 multiplexers and the timing of the RAS and CAS lines you can load a 16 bit address into the DRAMs - no CPU involved, just a long string of counters. Set up the high byte, drop the RAS,toggle the 157, set up the low byte, drop the CAS, job done. Any other way the DRAMs would have too many pins.
M

I don't know if it's me but seems a bit twisted to use a 'random accsess memory' to use it secuentialy... didn't?

what could be nice with this is to alternate the direction of RAM directions in order to get reverse delay, but I don't know where would it be...

JS

joaquins said:

I don't know if it's me but seems a bit twisted to use a 'random accsess memory' to use it secuentialy... didn't?

Click to expand...

There us far more uses for random access digital memory than serial. Analog memory is almost solely used for delay so sequential.

what could be nice with this is to alternate the direction of RAM directions in order to get reverse delay, but I don't know where would it be...

JS

Click to expand...

The beauty of 'random" access is that you can write the data in using one direction and read it out in another. Unfortunately you must deal with the fact that time only moves in one direction (from our reference plane) so a sample must be fully captured before you can read it out backwards. in practice you will have short backwards samples strung together in forward time.

A more practical use of RAM is to pitch shift signals by writing data into memory at one rate and reading it out slower or faster to shift pitch up/down. Again you end up with sample splicing issues since the pitch shifted samples are now longer or shorter than the original capture.

JR

PS Playing a tape or record backwards had to first capture the entire recording forwards.

I know, but this is how reverse delays works, each tap is repeted backwards in the next repetition, would be nice to make a 'deloreant' that could make what you are saying in revers and in shifting... diferent time speeds living together in the world,
'Imagine all the /time speeds/
Living life in peace' 8)

JS

joaquins said:

I don't know if it's me but seems a bit twisted to use a 'random accsess memory' to use it secuentialy... didn't?

Click to expand...

It was chosen for the design because it was easily available. There IS a sequential-access memory: it's called a FIFO. Of course to implement delay you need to have a counter which is set by the delay time. At some time zero, you start writing samples to the FIFO, and after the delay time counter expires, you start reading from the FIFO. So you've saved yourself one counter. The bad news back then was that FIFO chips were significantly more expensive than DRAMs. Actually, they still are.

what could be nice with this is to alternate the direction of RAM directions in order to get reverse delay, but I don't know where would it be...

Click to expand...

Reading backwards is simple in a modern design where the memory is accessed by an FPGA or a processor. The problem, as JR says, is that you have to capture the entire sample before you can start playing it back in reverse.

-a