1176 gain reduction stage Redesign, advice and help please.

Hi everyone, I was looking for some help with tweaking the gain reduction stage / preamp stage of the 1176.

I think I read on here some time ago, or maybe on Gearslutz some recommended ways of improving this stage.

The main improvement involved buffering the low side (Source) of the F.E.T. (BF245) with an invert of the top side (Drain)
this would mean that the F.E.T.'s Gate has DC on it only, instead of the the Gate voltage being modulated by some of the signal from the output of this stage, like it is at the moment.

It was also suggested that this inverting buffer have variable gain between 0.5 to 1.5 to minimize control feed through.
and also to Use a DC coupling around ground to avoid the need for a large value electrolytic capacitor (around 100uF in most designs)

I have based this new design on a op-amp based version of the 1176 I also found on here, just to make life easier.
at the moment I have not had any luck getting this to work, and I was wondering if somebody could point me in the right direction, or if any body else has tried a similar thing, or even if people have better improvements.

the last improvement i remember reading was to buffer the control voltage signal using a low-leakage JFET buffer in order to help stabilize it.
I am not sure where to begin with that.

any advice people can offer would be very much appreciated.

thanks.

R12 is a very heavy load on the node.

Clever concept though.

It does double the audio voltage *across* the FET, which probably means running half the signal level, 6dB loss of S/N? (Not to mention that TL07x hiss will overwhelm JFET channel hiss.)

I don't see what VR1 does now?

thanks for the reply.

if R5 VR1 and R6 were replaced with a 10K trim pot then this could be used to amplify the signal level.

would using something like a NE5534 or NE5532 be better suited for this?

and perhaps using 1k for R12 and R13?

and perhaps using 1k for R12 and R13?

Click to expand...

NO! A load of 1K would make the situation even worse!
It would cause a permanent attenuation of 1/28 or 33 dB!!

> would using something like ...
> and perhaps using ....

The gaps in your understanding are too big to fill though a cyber-forum.

Real-world experience is very helpful.

Go ahead and try your changes. With care, you won't blow-up many parts, and these parts only cost a few cents. For a few dollars and in a few days you will know more about JFET limiters than a 4-year engineering student.

I plan on making a few prototypes in order to gain a better understanding of exactly whats going on.

Just waiting for some components to arrive before I can start building it.
I have made some changes to my original concept though. I now plan on having the inverting buffer after the gain stage,
so that the top of the FET sees exactly the same as it was seeing in the original design.

I also plan on using a much higher quality op amp, such as the LME49720.