5V TTL input to FPGA LVCMOS25
« on: November 30, 2013, 03:53:17 AM »
How do you connect a 5V TTL to FPGA logic input LVCMOS25?  ???

I'm implementing DannyW's ADAT receiver code with my FPGA, but I bought the wrong optic receivers.

It's true that I can use them for S/PDIF, and get new 2.5V TTL receivers like the Everlight PRL135 series, but I just wanna know if there's a working solution that I can try.

I read about this issue in a forum, and the poster suggested a couple of tricks like using a limiting resistor or a diode in series, but he also mentioned that he's not sure if they are suitable for a data transfer rate beyond 1MHz (ADAT is faster than that)


jdbakker

Re: 5V TTL input to FPGA LVCMOS25
« Reply #1 on: November 30, 2013, 02:14:35 PM »
Something like http://www.ti.com/product/sn74lvc1g125, with a VCC of 2.5V. The LVC series is 5V TTL compatible even when run at lower supply voltages, and should be available pretty much everywhere.

JDB.
[there are lots of ways to skin this particular cat. I'd not go for series resistors or dropping diodes; modern FPGA input structures tend to not be too happy with those. If you don't have the patience to wait for another mail order to come in, I'd sooner use a resistive voltage divider (1k+1k?), or an NPN transistor in common-base, or...]

Re: 5V TTL input to FPGA LVCMOS25
« Reply #2 on: December 04, 2013, 04:51:47 AM »
Guess what? Not available everywhere apparently.

The local suppliers here only have, 74HC125 (CMOS input) and 74HCT125 (TTL input), in DIP-14 package.

Andy Peters

Re: 5V TTL input to FPGA LVCMOS25
« Reply #3 on: December 04, 2013, 02:34:18 PM »
Guess what? Not available everywhere apparently.

The local suppliers here only have, 74HC125 (CMOS input) and 74HCT125 (TTL input), in DIP-14 package.

Not sure where you're located, but the parts (leave the "SN" prefix off the part number to see other vendor options) are widely available.

Note that the '1G125 is a single bit and has a tri-state output. If you just need unidirectional level shifting, the 74LCV1G17 is what you want. If you need more bits then there are LVC variants of the '244, the '245 and the '541. See here for some possibilities.

The "Little Logic" parts are obviously not available in DIP.

HC isn't specified at 2.5V so no guarantees.

-a
"On the Internet, nobody can hear you mix a band"

Re: 5V TTL input to FPGA LVCMOS25
« Reply #4 on: December 04, 2013, 09:20:30 PM »
I always leave out the vendor prefix. And I always look for a pin to pin and function compatible replacement at the same time. No worries about getting a wrong part there :)

I found out that I can change the IO standard from LVCMOS25 to LVCMOS33 by modifying the user constraint file, or alternatively, use pins which have this standard by default. The Xilinx Spartan 6 FPGA family datasheet listed them in a neat color coded table 8)

As for the 74HC125 and 74HCT125 that I got from the vendor, they are made by NXP. From the datasheet,
74HC VCC in = 2V to 6V
74HCT VCC in = 4.5V to 5.5V
Both has output voltage of 0V to VCC.

Andy Peters

Re: 5V TTL input to FPGA LVCMOS25
« Reply #5 on: December 05, 2013, 11:23:27 AM »
I always leave out the vendor prefix. And I always look for a pin to pin and function compatible replacement at the same time. No worries about getting a wrong part there :)

OK, just checking.

Quote
I found out that I can change the IO standard from LVCMOS25 to LVCMOS33 by modifying the user constraint file, or alternatively, use pins which have this standard by default. The Xilinx Spartan 6 FPGA family datasheet listed them in a neat color coded table 8)

You have to:
a) MAKE SURE THAT VCCO for the bank has the supply voltage you need.
b) The IOSTANDARD in the constraint file has to be compatible with the actual supply voltage.

So if you set the IOSTANDARD on the pins to LVCMOS33, you must also provide a 3.3V supply to that pin's bank's VCCO pins. Just changing the IOSTANDARD isn't sufficient.

Quote
As for the 74HC125 and 74HCT125 that I got from the vendor, they are made by NXP. From the datasheet,
74HC VCC in = 2V to 6V
74HCT VCC in = 4.5V to 5.5V
Both has output voltage of 0V to VCC.

Right, but it's not as simple as it seems. The issue is mating 5V logic to the FPGA's lower-voltage pins.

If you choose the HC part and give it a 2.5V rail, it's not going to like a 5V input because the inputs are spec'ed to have a range from 0 V to VCC. So the inputs blow up.

If you choose the HC part and give it a 5V rail, its output will swing to 5V, which is bad for the FPGA's pins which don't tolerate 5V and anyways are outside of the bank voltage range.

The LVC parts tolerate a 5V input with a lower-voltage rail.

-a
"On the Internet, nobody can hear you mix a band"

Re: 5V TTL input to FPGA LVCMOS25
« Reply #6 on: December 06, 2013, 01:44:00 AM »
You have to:
a) MAKE SURE THAT VCCO for the bank has the supply voltage you need.
b) The IOSTANDARD in the constraint file has to be compatible with the actual supply voltage.

So if you set the IOSTANDARD on the pins to LVCMOS33, you must also provide a 3.3V supply to that pin's bank's VCCO pins. Just changing the IOSTANDARD isn't sufficient.

All I/O banks, are powered by the 3.3V supply rail.

Quote
Right, but it's not as simple as it seems. The issue is mating 5V logic to the FPGA's lower-voltage pins.

If you choose the HC part and give it a 2.5V rail, it's not going to like a 5V input because the inputs are spec'ed to have a range from 0 V to VCC. So the inputs blow up.

If you choose the HC part and give it a 5V rail, its output will swing to 5V, which is bad for the FPGA's pins which don't tolerate 5V and anyways are outside of the bank voltage range.

The LVC parts tolerate a 5V input with a lower-voltage rail.

In that case, I will get the LVC instead. Thanks Andy! ;D ;D ;D

BTW, what if I use the BSS138 / 2N7000 N channel MOSFET based logic level converter? Will this work in place of 74LVC1G125? Because actually, I have one that I used a while back for messing around with Arduino.
« Last Edit: December 06, 2013, 01:58:47 AM by chilidawg »

Andy Peters

Re: 5V TTL input to FPGA LVCMOS25
« Reply #7 on: December 06, 2013, 11:59:12 PM »
You have to:
a) MAKE SURE THAT VCCO for the bank has the supply voltage you need.
b) The IOSTANDARD in the constraint file has to be compatible with the actual supply voltage.

So if you set the IOSTANDARD on the pins to LVCMOS33, you must also provide a 3.3V supply to that pin's bank's VCCO pins. Just changing the IOSTANDARD isn't sufficient.

All I/O banks, are powered by the 3.3V supply rail.

Then why did you mention "How do you connect a 5V TTL to FPGA logic input LVCMOS25?" in the first post in this thread? If VCCO is 3.3V then the IOSTANDARD set in the UCF must be compatible, such as LVCMOS33, LVTTL, etc. LVCMOS25 won't work.

Quote
BTW, what if I use the BSS138 / 2N7000 N channel MOSFET based logic level converter? Will this work in place of 74LVC1G125? Because actually, I have one that I used a while back for messing around with Arduino.

That sort of thing is designed to do level shifting for the bidirectional open-drain I2C bus. I've used the PCA9306 to do that and it works. But if you're doing a unidirectional level translation, the LVC part costs about the same as the MOSFET and it just works.

-a
"On the Internet, nobody can hear you mix a band"

Re: 5V TTL input to FPGA LVCMOS25
« Reply #8 on: December 07, 2013, 03:28:25 AM »
Quote
Then why did you mention "How do you connect a 5V TTL to FPGA logic input LVCMOS25?" in the first post in this thread? If VCCO is 3.3V then the IOSTANDARD set in the UCF must be compatible, such as LVCMOS33, LVTTL, etc. LVCMOS25 won't work.

Sorry, sorry! When I asked, my I/Os were definitely set to LVCMOS25. It was a mistake at my end because I didn't know about adding IOSTANDARD to the pin assignment.

Andy Peters

Re: 5V TTL input to FPGA LVCMOS25
« Reply #9 on: December 08, 2013, 09:35:48 PM »
Quote
Then why did you mention "How do you connect a 5V TTL to FPGA logic input LVCMOS25?" in the first post in this thread? If VCCO is 3.3V then the IOSTANDARD set in the UCF must be compatible, such as LVCMOS33, LVTTL, etc. LVCMOS25 won't work.

Sorry, sorry! When I asked, my I/Os were definitely set to LVCMOS25. It was a mistake at my end because I didn't know about adding IOSTANDARD to the pin assignment.

Ah, yeah. If you don't specify a default IOSTANDARD for a pin, the Xilinx tools default to LVCMOS25. This causes all sorts of fun errors, such as when you constrain other pins in the bank to a non-2.5V IOSTANDARD and you forgot to do it with that pin you just added to the design.

-a
"On the Internet, nobody can hear you mix a band"


Re: 5V TTL input to FPGA LVCMOS25
« Reply #10 on: February 02, 2014, 09:04:55 AM »
Finished the ADAT receiver board design. No assembly yet.

Didn't use 74LVC1G125 because I couldn't buy one. Lame, I know :(
Picked 74HC4050D from NXP for the unidirectional 5V to 3.3V level shifting job.

Added I2S transmitter code and SMUX support to the ADAT receiver code.

Made two DAC boards.

A : TI PCM1691 in hardware mode (8 channel 24 bit I2S format). 2V RMS output buffer op-amps are ON Semi MC33074.
B : 4x ESS ES9023P (8 channel 24 bit LJ/I2S format). Integrated 2V RMS output buffer.