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Ian MacGregor

Well-known member
Joined
Jun 3, 2004
Messages
280
Location
Echo Park, Los Angeles, CA, USA
Hi All,

First off I want to say thanks again for the help with my last lab, it worked perfectly and the TAs were very impressed with the performance of the circuit. Anyway, we have been working on Lab 2 and since we had a pretty good discussion about the last lab, I figured I'd post our "still in design/test" schematic and a few questions.

First, here's a link to our Lab requirements

And here's a link to our first design

It is basically a differential stage (with Current mirror to provide better CMRR), a common emitter stage for the bulk of our voltage gain, and an emitter follower stage driving a push pull output stage.

We breadboarded our circuit tonight, and we are having problems with DC bias voltages starting with the voltage on the collector of Q1 (it is -0.5 VDC). The large voltages on our schematic are what we designed the bias to be, not what we are measuring it to be. The bias points for the differential stage look pretty good. The push pull stage is off as well, we are trying to design for 0 VDC at Vout (8 ohm resistor load), but right now we are getting a negative voltage of about a volt at Vout.

Any ideas? We felt pretty confident when designing this circuit, although it is our first mulit stage design. Seems kinda gnarly to go from a design with one tranny, to a design with 10+!!

Thanks!!

Ian
 
> Seems kinda gnarly to go from a design with one tranny, to a design with 10+!!

2 points off for a PDF that I can hardly read. I have to zoom to 400% to read part-values, but zoom out to 150% to see where they go. Dunno why that is.

R4 R5 R6 R7 are four resistors where two would do.

What is your AC gain? Or rather, what do you think it would be if it worked at all? Looks to me to be well in excess of the spec. They still didn't teach feedback?

Why does it say "0VDC" on the output? Transistors can't read diagrams. They don't know that you want the output to be 0VDC. (It isn't actually in the spec, either, but I assume you know it needs to be in the neighborhood of zero to meet other specs.)

There's a tip in the assignment: you can use a few caps, and need not be flat below 200Hz. You have designed an amp flat to DC. This is "better", but in audio not necessarily. Caps are useful crutches, and in audio they are often needed for real-world reasons. (That said, I do see a route to a reasonably stable DC amp to meet all specs.)

I just did a rough estimate of Q1 collector voltage, not knowing the Vbe and other parameters, and get "6.1V less than +5V". Which is within 10% of what your breadboard says, and quite different from where you should be after doing your homework. The only way I can get plausible voltage into Q8 Q5 is to assume several transistors have Vbe up around 0.9V, which is not likely at these currents.

Do you see that you will have a hard time pulling 8 ohms up to a +3V peak? My rough-calc says it will just-barely-maybe touch +3V peak. Except at that point, Q1's gain is down to 10% (33% counting the emitter resistor) so it needs gross overdrive to get there. 3V peaks from 5V supplies with a low-Z load is not an easy task. You have more important problems first, but keep that in mind when considering alternative topologies.

Your choices of standing currents seem good. Each stage runs at somewhat higher current than the one before it.

Did you calculate K or are those resistors just guesses?

What bothered me about this assignment is: it is really two problems. CMRR, and power output. In a non-academic project, I would do it as two pieces: a diff-amp and a power amp.

The spec leaves room for "creative interpretation". No input impedance is specified? Then the design is simple: a 1:15 transformer. Boom, done. Gives voltage gain of 15, the frequency response should be easy, the CMRR can easily be over 40dB or 60dB ("100dB"??? you won't even be able to measure that on a typical lab bench!). Power supply drain is zero, way-cool. Thermal stability is "hunk of iron" steady. So what if it has input impedance of 0.04 ohms? If the prof cared how bad you loaded his sources, he'd have put that in the spec. (However in practice, you might have to bring your own 0.04 ohm buffer to prove your design to the TAs.)
 
2 points off for a PDF that I can hardly read. I have to zoom to 400% to read part-values, but zoom out to 150% to see where they go. Dunno why that is.

Hmm... I am using PowerLogic for schematic capture. I just took a sec and tried to change the height of the part values/ref #'s and I couldn't. I need to look into that one.

R4 R5 R6 R7 are four resistors where two would do.

Ok... I understand.

What is your AC gain? Or rather, what do you think it would be if it worked at all? Looks to me to be well in excess of the spec. They still didn't teach feedback?

After our AC analysis, we figured our AC gain would be pretty damn close to 15. The gain should be: differential is 1, the CE is 18.75, the EF is 1 and the push pull is 0.8. Did we make a major error in gain calculation? Oh yeah, and we still haven't been taught feedback for this sort of application. Tho, the way I see, it is an opamp, right? Maybe we should we design for a large open loop gain and then use negative feedback (like with a IC opamp) to bring the gain down?

Why does it say "0VDC" on the output?

I just figured it would help if I put some of the bias values we "tried" to design for.

I just did a rough estimate of Q1 collector voltage, not knowing the Vbe and other parameters, and get "6.1V less than +5V".

Ok, this is where I start to get lost. Knowing that the base of Q1 is biased correctly (it is currently around -4.2V), we can't figure out why the collector of Q1 is so low. The emitter current is about (5V-4.85V) / 76 ohms ~ 2mA. This should be damn close to Q1's collector current. So the current through R13 is Q1's Ic + Q8's Ib. Therefore, Q8's base current has to be around 1mA to get the 6V drop that we are seeing. This seems wrong to me. Shouldn't the base current of Q8 be around beta times less than its collector current (which is set by the CCS @ around 20mA)? I have a feeling this is the part of the circuit where we have really messed up.

Did you calculate K or are those resistors just guesses?

I think you mean "did we calculate the resistor values"??? And yes, we did, for some of them, I just substituted the closest 5% standard value.

No input impedance is specified? Then the design is simple: a 1:15 transformer.

hahah.. coolest idea ever. I believe that I will take a transformer in and show that to the TAs first, just to see their reaction.

Oh yes... and our CMRR requirement has been changed to 80dB.

Thanks again PRR, I feel like I am learning alot, or at least will by the time I've got it workin'.

Ian
 
> "did we calculate the resistor values"???

No, I meant the thermal stability factor "K" in the bottom of the assignment. Your solution isn't wrong, but I don't get the same answer.

> I just substituted the closest 5% standard value.

But think when you do that. A 5% error in the input, times the gain of 15-20, can be a very large error at the output.

> I believe that I will take a transformer in

A working 0.03:8Ω 0.4W tranny is a very special part. If I had to do one overnight, I'd take a 10VA power tranny with a 12V winding, one with enough space between winding and core that I could thread some more turns around the outside of the winding. I'd wind 10 turns of any handy wire, drive the "12V" side with a few volts at maybe 400Hz, and read the volts on the new winding to get the ratio. Figure how many turns give the desired ratio, find the very biggest wire that can fit that many turns. We'll want much-less than 0.03Ω of winding resistance, so it will be wall-wire stuff. Peel the plastic and paint with nail-polish for insulation.

> our CMRR requirement has been changed to 80dB.

OK, but still absurd. How big is 80dB? 10,000:1! How will you test this? See if the output is under 1V when the common-mode input is 10,000V? THAT would take heroic design! Or apply a nice 1V CM signal and look for 100 microvolts on the output? And note that "something" in your design has to be matched to 1/10,000 (0.01%) accuracy. BTW, what is your common-mode input range? Would it function in my big-room where the upstairs ground is about 5VAC away from the downstairs ground?

> the base of Q1 is biased correctly (it is currently around -4.2V), we can't figure out why the collector of Q1 is so low. The emitter current is about (5V-4.85V) / 76 ohms ~ 2mA.

Why do you think Q1's Vbe is 4.85-4.2= 0.65V? That may be true, but is HIGHLY variable. If you want to know the emitter current, use your battery-power DVM to measure the 75 ohm resistor voltage directly. (If they won't let you un-ground the DVM, measure the emitter voltage and the supply voltage with good precision, and subtract.)

My analysis: R11 Q7 R10 current is close to 1mA. So there is about 2.8V across 1.5K R9, suggesting 1.87mA in Q3. This splits (equally?) to Q2 Q8, so Q8 is 0.933mA. R8 is 1K, so it has 0.933V on it. Taking your 0.65V Vbe Q1 guess, R12 has 0.283V on it, is 75 ohms, 0.283/75= 3.78mA. This flows in R13, which is 1.8K, so 1.8K*3.78mA= 6.8V. This pulls down from +5V, so Q1 collector is 5V-6.8V= -1.8V.

Are you still using the R4 R5 R6 R7 array, of 5% resistors? Worst-case, this can inject 0.5 Volt of differential input DC. Another 5% error in R2 R3 makes it worse (though I note you seem to have picked 1% values here.... why? It does not help CMRR).

> Maybe we should we design for a large open loop gain and then use negative feedback (like with a IC opamp) to bring the gain down?

That is how I would do it. And nearly any other designer with more than a semester of transistor-smoking under their belt, unless there were some compelling reason to do otherwise. Not only to set signal gain, but to set DC levels without tedious calculations and those annoying parameter tolerances.

Is this an open-book exercise? There is a very common 1-opamp differential input design that, if you opened-up the open-loop gain, would set DC level and AC gain in four resistors. Quick tip: feedback over several stages can be unstable. Keep that input stage working at quite low gain, and take most of your gain in the second stage.

Also: 8Ω power-amp designs are eveywhere. Though not too many discrete +/-5V designs, a look at how other designers have driven speakers before you might suggest another output topology.

Oh, BTW: your negative-swing won't be 3V either. Why are all your current-mirror emitter resistors so big? Two same-type same-lot transistors at the same current will match to 50mV, probably better than 20mV. At different currents, you should be able to estimate the offset voltage, and for practical ratios it will be under 20mV (why?). So wht does R17 have 2 Volts across it?
 
OK,
So after a few circuit changes, we have it working about at spec. The major changes we made are:

(1) Used Emitter degeneration on the CE stage to change DC levels (without changing AC gain). We basically put a trim pot (bypassed wtih large capacitor) as the emitter degeneration. We then change the pot until the output voltage sits at 0V DC (at idle). I'm kinda thinking this is the reason you gave us the hint that we could use capacitors if we want. Am I on the right track?

(2) Changed the resistor values of the second CCS (biasing the EF stage). We re-designed the CCS to that it "eats up" a lot less voltage, and therefore the resistor values were much lower. Thanks for the tip PRR.

Our gain is pretty much 15, we haven't tested CMRR yet.

I still feel that I would have liked to have used feedback but we don't have very much time before this is due, and a complete redesign would probably take too much time.

Again, thanks a ton for the help. I've already taken a look at our 3rd (and last lab) of the quarter. It looks pretty intense. I'm sure I will have more questions soon!!

Thanks,
Ian
 
> put a trim pot (bypassed wtih large capacitor) as the emitter degeneration. We then change the pot until the output voltage sits at 0V DC (at idle).

Well, OK.

I'm sure you see that, if you make a million of these, and pay somebody $0.10 each to trim, the production costs would justify MUCH more design time. But the economics are backward here (do ONE, once, NOW, and move on to chapter 3).

How stable is it? Get a good finger-grip on Q1 (a few degree temperature shift), how much does the output drift?

Change Q1 (or any transistor) to another of the same type. Re-trim?

I see a pattern of using emitter resistors. Just FYI: there are often better ways to set bias and gain in low-level circuits.

> Our gain is pretty much 15, we haven't tested CMRR yet.

In the low audio band, your approach should give excellent CMRR.

> I would have liked to have used feedback but we don't have very much time before this is due, and a complete redesign would probably take too much time

What I wuz thinking:
Ian-2.gif


There are real practical issues with this one (heavy and uneven input loading, will die if shorted {yours will too}) but good enough for Lab.
 
Ahhh... very cool. We are still having problems with gain stability (as you have forseen). We may have to go with feedback. I'm gonna check it out on paper and maybe breadboard it up after my partner comes back from Lab with results.

Thanks

ian

EDIT
Quick (hopefully) question: I'm in the middle of analyzing/figgerin' out your circuit PRR. I've pretty much figured out that the differential stage has a gain of about 24 (?) and that the gain of the CE stage is very high (Ro of the CS / re ), right?? Anyway, how does one figure the saturation cutoff voltages throughout the circuit? Before feedback, I would figure out the cutoff/sat levels of the differential, then multiply that by the voltage gain of the following stages. I would continue stage by stage until I found the smallest value, and use that value*2 as max peak-peak output. But with the high gains of the CE stage and diff stage, do I continue the analysis in the same way?

Thanks again
 
On third thought:

Keep the emitter resistors in the input stage. The "Why?" analysis is not first-year nor trivial, and I'm unsure what a good value is. Try 50, try 500 ohms. Since you have resistors already, leave them there. If it is stable but the gain is 5% low and the CMRR sucks, go with lower input emitter resistors, but watch the scope for big fuzz (MHz oscillations).
 
Are you sure my scheme will DC-bias nicely? (I'm sure that either it will, or I've made some drawing error; but it isn't me who has to defend it to the boss/prof.)

> the differential stage has a gain of about 24(?)

Assuming Q1 has infinite Beta, I get 10 or so. With Q1 it can't be more than about 4. So (for reasons you may need Lab 3 to get into) you may not need input stage emitter resistors.

What is gain in Q1 stage? Assuming 8Ω load, I get "several hundred".

> how does one figure the saturation cutoff voltages throughout the circuit?

If your vision is clear, only one stage will be critical. If Q1 has high gain, then the output level of the input stage needed to smack Q1 around is so small that it isn't necessary to compte it. If Q1's current source load is "perfect", then Q1 collector can swing up to +5V and down to maybe -4.2V (see the advantage of not using emitter resistors?). The complementary emitter followers will swing 0.6V-1V less at the output. Distortion in Q1 is a real issue (compare Q1's Gm with output swung low or high), but was not specified.

Do you understand the feedback? (If not, do NOT turn it in for class.) It is possible that the output of the naked amp can (try to) swing big, but apply "illegal" voltage to the input stage which will put it out of operation. A different example: strapping output to the -IN terminal gives a unity-gain amp. The output can swing maybe +4V/-4V. But your original input stage can only swing up to maybe +3V (and maybe not that much), so the clipping level is set at the input, not the output. This tends to be a smaller problem when the total system has gain (input is less than output), but you can still get in trouble.

Looking to Lab 3: things make a little sense and a little confused. Why does Lab 2 need a great differential input, and has no input-Z spec, when used after a single-gang volume pot? And tutorial aside, I can meet that Lab 3's functional specs without an op-amp, in 3 transistors. The gain-shape spec does not need super-gain accuracy, and the requirements prohibit overall DC response. Give me a 9V battery, three NPNs, 4 or 5 resistors, and 3 caps.

The total system gain of 150,000 (103dB!) seems high too. Yes, a small speaker is a weak mike. And your speaking-speaker may also be weak. And the lab may be large, even deadened. Still I believe you are way up into acoustic feedback with that much gain.
 
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