Ian MacGregor
Well-known member
Hi All,
First off I want to say thanks again for the help with my last lab, it worked perfectly and the TAs were very impressed with the performance of the circuit. Anyway, we have been working on Lab 2 and since we had a pretty good discussion about the last lab, I figured I'd post our "still in design/test" schematic and a few questions.
First, here's a link to our Lab requirements
And here's a link to our first design
It is basically a differential stage (with Current mirror to provide better CMRR), a common emitter stage for the bulk of our voltage gain, and an emitter follower stage driving a push pull output stage.
We breadboarded our circuit tonight, and we are having problems with DC bias voltages starting with the voltage on the collector of Q1 (it is -0.5 VDC). The large voltages on our schematic are what we designed the bias to be, not what we are measuring it to be. The bias points for the differential stage look pretty good. The push pull stage is off as well, we are trying to design for 0 VDC at Vout (8 ohm resistor load), but right now we are getting a negative voltage of about a volt at Vout.
Any ideas? We felt pretty confident when designing this circuit, although it is our first mulit stage design. Seems kinda gnarly to go from a design with one tranny, to a design with 10+!!
Thanks!!
Ian
First off I want to say thanks again for the help with my last lab, it worked perfectly and the TAs were very impressed with the performance of the circuit. Anyway, we have been working on Lab 2 and since we had a pretty good discussion about the last lab, I figured I'd post our "still in design/test" schematic and a few questions.
First, here's a link to our Lab requirements
And here's a link to our first design
It is basically a differential stage (with Current mirror to provide better CMRR), a common emitter stage for the bulk of our voltage gain, and an emitter follower stage driving a push pull output stage.
We breadboarded our circuit tonight, and we are having problems with DC bias voltages starting with the voltage on the collector of Q1 (it is -0.5 VDC). The large voltages on our schematic are what we designed the bias to be, not what we are measuring it to be. The bias points for the differential stage look pretty good. The push pull stage is off as well, we are trying to design for 0 VDC at Vout (8 ohm resistor load), but right now we are getting a negative voltage of about a volt at Vout.
Any ideas? We felt pretty confident when designing this circuit, although it is our first mulit stage design. Seems kinda gnarly to go from a design with one tranny, to a design with 10+!!
Thanks!!
Ian