Distributing I²S over a long distance

Hi there!

ATM I'm in the development phase for a new device, which includes the interconnection of a 19" rack with a desktop remote control. I use a I²C connection for data transfer and control, powered by a msp 430 µC, which also provides the clock signal.

Right now, I'm at the point to deliver two stereo and one monosignal from one device to another, and ideally this will also take place in the digital domain, because i want some DSP filters included in the signal chain. So i crawl around the interwebs and i laid eye on the I²S standart. As far as my research goes, the standart only provides a few centimeters of distance.

My goal would be to distribute the signal over a cable about 5-10 meters...for I²C there are some buffers like the PCA9600 (http://www.nxp.com/products/interface-and-connectivity/interface-and-system-management/i2c/i2c-voltage-level-translators/dual-bidirectional-bus-bufferCA9600) available to shift the signal to a higher voltage level, so that the distribution over a long distance is possible. I've talked to another developer, and he managed to succsessfully distribute the I²C signal over 20m with this 'trick'.

My question to you guys would be: are there any similar methods for I²S?

I've found some level buffers which are able to shift the signal level and have enough lanes, like the MAX13030E (https://www.maximintegrated.com/en/products/interface/level-translators/MAX13030E.html), but i'm not sure if there are certain limitations, because there is no explicit IC for this problem available (at least i did't found something)...

Does anyone around here have experience with I²S and could give me some advice?

Thanks in advance!

Tomess

Hi,

transmitting i2s over a long distance is not easy.
Did you think about converting the i2s to S/P-DIF / AES3 on TX side and converting back to i2s on RX side?
This you can easily do with chips like CS8406, CS8416 etc.


Raphael

If you provide a connection with reasonably well defined impedance (e.g. ribbon cable), LVDS drivers/receivers should work very well.

Samuel

twisted pear audio's teleporter does just that, you can use it as a starting point for your own....

http://www.twistedpearaudio.com/digital/teleporter.aspx

- michael

Hey everyone!

Thanks for your quick replies! 

@rkn80:

thanks for your suggestion, i'll definetly look deeper into it tomorrow! But converting an already converted signal (ADC) seems to generate more problems, because there have to be some additional clocking, i guess... And it is already kind of hard to deliver two different clocks around because of possible ESD problems and other conflicts...

@Samuel & Audiomixer:

Thanks for your suggestion, i had already took a look at this differential method, but i was afraid of using so many lanes, since there will be two AD and two DA convertes included, which have to communicate with each other at the same clockspeed.

I've read, that there will be a delay of a few ns when using the LVDS method, and i'm not shure if this fact will mess up the general timing and sync, since i wanted to use the same MCLK, BCKL and LRCLK for every ADC and DAC in the system...

I was thinking about using a HDMI Cable to deliver the signals, since it is made for HF data signals and kind of well shielded...

There is a chinese guy who provided a hack for his own products (I²S over HDMI):

http://www.audio-gd.com/Pro/diy/I2Skits/I2SEN.htm

Could this spare me the pain of implementing the LVDS option? HDMI Cables are cheap and kind of made for I²S distribution, if i've read it right...looks like a convenient solution to myselfe...what you guys think?

Cheers, Tomess

You would have to resort to specialized techniques (e.g. ECL) to get lower delay than with LVDS.

Samuel

Tomess said:

@samuel:
Thanks for your suggestion, i had already took a look at this differential method, but i was afraid of using so many lanes, since there will be two AD and two DA convertes included, which have to communicate with each other at the same clockspeed.

I've read, that there will be a delay of a few ns when using the LVDS method, and i'm not shure if this fact will mess up the general timing and sync, since i wanted to use the same MCLK, BCKL and LRCLK for every ADC and DAC in the system...

Click to expand...

LVDS is the way to go.

First thing to realize is that while MCLK is related to the I2S signals (BCLK, LRCLK, data), its phase relative to those other signals is not important. 

Next, realize that if you run all of the signals through LVDS drivers and then receive them some distance away, as long as the cable lengths are matched (such as with an HDMI cable, or a Camera Link cable, or even a CAT-6), the delay for all signals is the same.

Finally, look at the spec for I2S. It is like SPI and other moderate-speed synchronous serial data scheme, where data are driven out on one clock edge and captured on the next opposite clock edge. And since the prop delay through all of the drivers and receivers is the same, and since the cable delays for all lines are the same (important!), the latency of the whole system doesn't matter, and the clock out on one edge/capture on the other design of SPI and I2S ensures that you always meet setup and hold times at the receive end.

There is a chinese guy who provided a hack for his own products (I²S over HDMI):

http://www.audio-gd.com/Pro/diy/I2Skits/I2SEN.htm

Could this spare me the pain of implementing the LVDS option? HDMI Cables are cheap and kind of made for I²S distribution, if i've read it right...looks like a convenient solution to myselfe...what you guys think?

Click to expand...

His pinout suggests differential drive, so my guess is the SOIC-16 chip on the driver board is a DS90LV031 LVDS driver and the receiver is the DS90LV032 receiver. I don't see any particular reason why it shouldn't work, although you want good signal integrity getting the signals from your board to his adapter. You should just put the LVDS drivers and the HDMI connector on your board.

(edited for hopefully clarity.)

Hey Andy!

Thanks for your reply! I see, there is much to learn for me  I'll look deeper in the LVDS thing today! Maybe i'll come back with some questions regarding this topic!  8)

Thanks everybody, you're really helpfull!

Cheers, Tomess!

Hey @ all!

So, i've spend the last few days to get deeper iton this LVDS thing, and i've to say: this is a realy neat technology!  8)

There's only one thing that make me a little nervous, and just to be shure i'll ask you guys again:

I want to have two Clocks in my system, 400 kHz for I²C in fast mode and 12,228 Mhz (256 x 48 kHz) for my AD/DA combinations (Texas Instruments PCM 1802 to Analog Devices ADAU 1701 & ADAU 1761 to Texas Instruments PCM 1791 A )

For example:

I Send the 12,288 Mhz Clock over the LVDS Network to the PCM 1802. The fastes LVDS Blocks that i found have a maximum latency of 4 ns (serial to differntial and back).
The PCM 1802 works in master mode, which results in generating the I²S clocks (BCLK and LRCLK) for the slave. The slave is the ADAU1701 on the other board.
I send the I²S clocks + data back over the LVDS Network to the ADAU 1701, so there is another latnecy introduced to the system, which will be another 4 ns max. (If the numbers in the datasheet are correct, of course  : ).
The ADAU 1701 needs also a 12,288 MHz master clock, which is generated on the same board.

Which results to my question:

Is it a problem to use this clock direktly, because the I²S Signal will be 8 ns late (max.)?

I mean, theoretically, the max. frequency in my system could be 1/8ns = 125 MHz,  bevor a problem could occur. So i'm approximatly 5 times slower with my system clock, and this should not be a problem.

Am i right with this consideration?

Cheers, Tomess

If I do understand you correctly you want to have a local 12.288 Mhz clock at the receiver? seems odd to me, you should send all I2S signals from the master, otherwise you need to SRC (samlerateconvert at the input of your far end). since the'll have the same latency on all I2S signals it's not an issue any more.  do you want to send I2C also over LVDS? LVDS is not bidirectional, is it? so you would have to send that (SDA SCL) directly, you might have to reduce the speed depending on your cable lengths,  no worries.

- Michael

Tomess said:

Is it a problem to use this clock direktly, because the I²S Signal will be 8 ns late (max.)?

I mean, theoretically, the max. frequency in my system could be 1/8ns = 125 MHz,  bevor a problem could occur. So i'm approximatly 5 times slower with my system clock, and this should not be a problem.

Click to expand...

Just a heads-up on this part. That number is correct for -zero- cable delay, which is not true in practice. Cables have a finite propagation delay, which will be (for the length of 5 to 10m you mentioned earlier in the thread) dominant compared to the LVDS conversion.

A rule of thumb I use for coax cable is about 5 ns delay per meter, which gives 25-50 ns extra on top of your LVDS conversion delay. This will vary with cable geometry, so it won't be exact, but it's a ballpark figure generally good enough for initial design.

So, with a 12.288 MHz clock, if you add in those 25-50ns, times two (round trip back and forth), you already are over your clock period.  (Even though what really matters here is BCLK, as data & LR is linked to it - as Andy Peters pointed out, you don't really even care about MCLK's phase w.r.t. other signals for what concerns the ability to correctly receive I2S data).

My personal opinion is, -if- your system has all the ADCs in box A and all DACs in box B, then put a local oscillator in A, run the A side as master, generating MCLK, BCLK, LRCK, and data, and feed all four of those signals to box B using the HDMI cable.

That way you should be able to build a system that is more robust with variations in cable length (within limits - I don't know the specs for interpair skew of an HDMI cable). If you start bouncing signals back and forth, you are going to run into problems when cables get long(er).

I think this would be the right moment to ask for a block diagram, showing the boxes and the distribution of the AD / DA converters within.... a DaveCAD(r) is totally sufficient...

if you have audio going back and (AND is the key issue here) forth then a single masterclock will no cut the mustard, due to latency. in that case you probably need to investigate multiple time domains in your DSP with sample rate conversion....

cheers,

Michael

Hello. This is something I have wrestled with, and I just realized and tested the answer.

If you use 1.27mm ribbon cable, and interleave a few ground wires, then you can easily run stereo I2S over 20m without any change in the buffers or levels.

However, make sure you put a 130-150 ohm resistor across each signal to a ground pin at the very end of the line.

The last post to this thread was in 2015, but welcome to the forum.

JR