Can it be done? sure... but.... (given caveats above)
some things to consider:
Since this is ADC, DAC, USB, AES-EBU or whatnot, this is getting into Signal Integrity high-speed digital design (like RF phenomena) on PCBs.... 6MHz to 12MHz or even 25 MHz / 33 MHz might be required depending on chipset selected and ADC oversampling rates.....
high-speed digital design on PCB is not intuitive at first, but with experience can be enlightening.
I'd skip any notions of 2-layer PCB for (un)obvious reasons; four or even six layers are likely. Yes, some ADC/DAC chip manufacturers may have reference designs for two-layers (for economy, for evaluation in a _laboratory_ environment) that may be copied, but be mindful of electromagnetic interference (EMI) notions, especially with high gain or high impedance analog electronics in the same room... a 4-layer board with proper planes and high-speed design motifs (matched impedances) can knock down EMI by 20dB or so (rule-of-thumb)....
High-speed digital PCB designs work best with a solid (physically uninterrupted) ground plane underneath high-speed digital traces, for any semblance of EMI reduction. This is because the "return current" of these high-speed signals will desire to flow (or concentrate) directly underneath the actual signal trace on the other layer... this is the path of least impedance, usually, the path of least inductance....two-layer PCBs physically constrain the design such that at some point, power, a connector pin-field, or some other signal will need to cross under the high speed trace (and physically interrupt the contiguous ground plane) thus increasing the path of inductance for the "return current" that would have to go around the obstacle (pin-fields on connectors also can break up a ground-plane).. This is also a contingency recipe to create electromagnetic interference...
keeping analog and digital ground planes separate is another interesting topic...
Also PCB dielectric material and THICKNESS dictate some other RF/high-speed parameters (see below) AND trace width (keeping in mind limitations of PCB fab house for allowable minimum trace width).... keeping in mind that usual overall thickness for standard PCBs might be 0.062 inches (1.575mm) thick, so the PCB layer stackup should be considered ahead of time....
With high speed digital, the frequency is important, but also the rise time (how sharp the digital signal square waves are) is extremely important. The sharper the rise time, the more harmonic frequency content that must arrive from "transmitting output of logic gate on chip" to the "receiver input of logic gate on another chip".. For example, some FPGAs have slew-rate limiting on their digital output pins for this reason (to slow down rise time, and moderate some design requirements of high-speed digital traces / power requirements)...
PCB traces at high-speed/frequency are Transmission lines that have a characteristic impedance and like to see that "RF" energy be terminated into matching impedance; max power transfer motifs as well... Otherwise reflections (or ringing) occur, which can cause timing or threshold level errors in the digital system...
Splitting of PCB traces (e.g., multiple tee's or branches on a clock line for distribution of the clock to multiple chips) is tricky... each branch or split needs to be mindful of total impedance, reflection, etc.... or use a clock buffer/distribution chip, at the expense of perhaps some noise/jitter, power draw, layout etc....
Measuring with oscilloscope probes also involves different techniques. The "long" flying ground clip-lead on the probe is usually bad for measuring high frequency stuff due to loop area, but can be good for sniffing... Usually taking the cap off of the scope probe to expose the ground ring (and design the PCB to be probed with oscope probe tip cap removed, with ground nearby for the ground ring)
Also, typical 'scope probes cannot probe a crystal directly because the probe impedance is too low. (and stops the crystal from oscillating)...
indeed, 12MHz square wave will have harmonics that hopefully the scope can capture or measure within its bandwidth
Arrival time (and skew) topics are also important for high-speed digital signals... it does take a finite time for a signal to travel on PCB traces (and is different propagation times for outer layer PCB traces versus inner layer PCB traces)....
Vias have (parasitic) inductance.... ground planes in sensitive areas may increase parasitic capacitances, that are not represented in the schematic (hence the term parasitic)... these may not be critical at lower "high-speed" frequencies, but....
Signal integrity analysis tools typically use IBIS models (which are different than SPICE models)... These tools are used before PCB layout (schematic design time) to figure out termination schemes on high-speed nets... They also have post-layout capabilities to tune routing and terminations.....
<shameless plug> I use Altium, but am not employed or involved with any of the below links....
http://www.altium.com/video-altium-presents-signal-integrity
https://www.youtube.com/watch?v=FXjVrYwSAGc
even 10MHz with a fast enough rise time can be considered high-speed...
</shameless plug>
Of course power (and decoupling capacitor with proper PCB layout, and decoupling capacitor TYPE - e.g., film, electrolytic with ESR and ESL, tantalum, ceramic etc.) is important, and higher frequency digital signals need to have their power sourced from the chips using the chips' power (and ground) pins... phenomena like ground bounce happens if the ground is feeble (conductance-wise), given also that the "ground" (reference voltage, especially for logic threshold concepts) bond-wire inside the chip from the pin to the silicon is a (parasitic) inductance, especially higher up in frequency...
decoupling capacitors have RF properties and resonances and help counteract trace inductance on power distribution traces....
Just some abbreviated random ramblings for high-speed digital design... concepts to look up on the Internet....
https://en.wikipedia.org/wiki/Signal_integrity
http://electronics.stackexchange.com/questions/75368/how-can-pcb-trace-have-50-ohm-impedance-regardless-of-length-and-signal-frequenc