JFET-based compressor question

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mr coffee

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Maybe I am just missing something obvious to others, but I've been wondering lately about the JFET attenuation, setup, and in particular whether paralleling JFETs and lowering the input attenuation resistor value might milk better noise performance out of the JFET compressor circuit, especially if the compressor's input ( signal source ) was only a volt or two to start with.

mr coffee
 
Two buys 3dB, four gives 6dB, nine makes 10dB improvement.

IF you can match that many JFETs!!

As with so many things: if your elders didn't think it was worth doing, it may not be.
 
Hi prr,

Thanks very much for your reply.

When you say,
"if you can match that many JFETS",
it makes me wonder, "matching with respect to what, or which, parameter(s)?" and "How close is necessary", and to some degree,  "Why is matching so important?"

I can see how Vpinchoff would need to be pretty close, but wouldn't the rest of it be relatively  unimportant?

What "negative effects" would\might be caused by rougher matching? I'm thinking of this on electric guitar where the JFET distortion tends to be acceptable, perhaps even desirable.

mr coffee

 
I am not aware of noise being the dominant problem with JFET shunt limiters. I would be more worried about linearity (distortion) but maybe that is just me. There are published techniques to cap couple some of the source audio signal into the gate (at around -6dB) to improve linearity.

This is a mature technology so many old designs to look at.

JR
 
> not aware of noise being the dominant

Signal level must be low, dozens of mV, for low THD.

Series resistor must be large, dozens of KOhms, for good attenuation.

Counting with thumbs, I get 2uV hiss and say 30mV signal, 83dB S/N. Good, but not always good enough. In a bar, the crowd noise may be only 30dB below the max the Marshall can make. In a concert, 90dB ambient to peaks is possible.

I'd say 95++% of "guitar" compressors have design flaws, so I'm not about to fret the abstraction. There are excellent mini-compresors now that we have THAT chips.
 
Thanks for  replies and considerations..

THAT VCAs are great building blocks, and their S/N is hard to beat. And when thinking in terms of cost-effective low-noise design,  they are probably the hands-down winner these days when looking to go beyond the age-old  Dyna Comp 3080  designs that continue to dominate the guitar effects world 40-plus years later.

The (relatively) newer "stompbox" offerings like the Boss CS-3, Carl Martin, etc., that represent the lower noise end of the  THAT VCA-based "stomp box" compressor market are far better noise-wise than the run-of-the-mill variety, although good old photocells still turn up because of their "sound", and they can be quite quiet as well.

But back to my original question about paralleling JFETs as a gain control element in a compressor.

Is JFET matching beyond Vpinchoff important for paralleling them?  If so, why?  In terms of what?

Thanks for any wisdom you may have to share.

mr coffee





 
mr coffee said:
Maybe I am just missing something obvious to others, but I've been wondering lately about the JFET attenuation, setup, and in particular whether paralleling JFETs and lowering the input attenuation resistor value might milk better noise performance out of the JFET compressor circuit, especially if the compressor's input ( signal source ) was only a volt or two to start with.
You have to think about how thet would reduce noise. Noise in a FET compressor is mainly due to the amplifier that makes up the signal after it's been attenuated in order to minimize distortion. Typically a single FET would be associated with a 10-30k  (1176 use 27k)resistor that defines the source impedance the make-up amp sees. The Johnson noise of a 20k resistor is 2.5uV; if the input stage is optimized, it will contribute the same, resulting in 3.5uV EIN, which, compared to the operating level there (let's assume -30dbu) results in about 80 dB S/N.
Parallelling the FET's won't allow a higher operating level, but will allow a reduction in source impedance. Let's assume 8 FET's in parallels, the series resistor would drop to 2.5k, EIN would be down to 1.2uV, provided the input stage is tuned for this lower source impedance. That could well result in a 9dB reduction in noise, but that would require all the FET's to react similarly to the control voltage, so not only the pinch voltage should be identical but also the Gm. It's feasible for DIY but not practical for manufacturing.
 
Thanks for the insights.

I follow how the reduction in impedance levels improves the S/N, and how difficult\impractical it would be to match 8 JFETs in a production environment for both Vpinchoff and transconductance. I'm aiming for a DIY project\experiment.

Since matching is always relative, any idea how variations might affect the performance of the paralleled JFETs in an attenuator application?

I'm imagining that the "slam mode" is probably more the sound I'm after, and I've never had  one on my bench to scope what level is hitting the JFET when this is the circuit configuration. Anybody already investigated\banged their head against this wall already?

Thanks to everyone for sharing their knowledge,

mr coffee




 
mr coffee said:
Since matching is always relative, any idea how variations might affect the performance of the paralleled JFETs in an attenuator application?
Assuming you achieve 10% matching (which requires either 16 trimpots or an incredibly tedious selection process from a batch of thousands FET's ), you may achieve about 7dB improvement instead of 9.
 
mr coffee said:
I'm imagining that the "slam mode" is probably more the sound I'm after, and I've never had  one on my bench to scope what level is hitting the JFET when this is the case.
mr coffee

The amplifier following the FET has a fixed gain of 26dB and this is followed by the output amplifier. Assuming the output of the 26sB amp is about +4dBu then the voltage across the FET, with no attenuation is below -20dBu or about 70mV. As the input signal rises, the FET control voltage reduces its resistance so the signal across the FET rises much less than the input signal does. Probably never exceeds 100mV.

Cheers

Ian
 
ruffrecords said:
The amplifier following the FET has a fixed gain of 26dB and this is followed by the output amplifier. Assuming the output of the 26sB amp is about +4dBu then the voltage across the FET, with no attenuation is below -20dBu or about 70mV. As the input signal rises, the FET control voltage reduces its resistance so the signal across the FET rises much less than the input signal does. Probably never exceeds 100mV.

Cheers

Ian
Overall gain after the FET is about 40dB (24 + 16), so for +4dBu output, the minimum level at the FET would be about 12mV, but the output pot is never at full whack, probably about 10-12dB down, so the level at the FET would be about 30-40 mV. With 100mV, the unit would be in crunch territory.
 
abbey road d enfer said:
Overall gain after the FET is about 40dB (24 + 16), so for +4dBu output, the minimum level at the FET would be about 12mV, but the output pot is never at full whack, probably about 10-12dB down, so the level at the FET would be about 30-40 mV. With 100mV, the unit would be in crunch territory.

If you look at the manual it suggests you start with the input and output controls centred, Assuming these are regular log pots with 20dB attenuation at the centre , this gives an overall nominal gain of 0dB. For a +4dBu input this makes the level at the FET -16dBu or about 120mV.

Cheers

Ian
 
ruffrecords said:
If you look at the manual it suggests you start with the input and output controls centred, Assuming these are regular log pots with 20dB attenuation at the centre , this gives an overall nominal gain of 0dB. For a +4dBu input this makes the level at the FET -16dBu or about 120mV.

Cheers

Ian
Center position is -24dB, according to FP legends, and suggested input level is 0dBu in the procedure, which computes at about 50mV.
 
abbey road d enfer said:
Center position is -24dB, according to FP legends, and suggested input level is 0dBu in the procedure, which computes at about 50mV.

Looks like we are iterating towards a stable end value!!

Cheers

Ian
 
Useful discussion for me - Thanks guys!

Most of the Application Notes I've read seem talk about using a signal level of up to  500 mv, across the JFET, albeit with 0.5% distortion and using 50% signal added into the JFET control voltage for distortion reduction - clearly a bit higher signal level across the JFET than the flagship models we seem to be primarily discussing here.

So perhaps a compressor that could tolerate less pristine distortion levels could have a much higher s/n ratio with perhaps fewer and less critically-matched JFETs? Even 1% distortion doesn't sound prohibitive if you are tracking guitar and not vocals. I'm not thinking of a general purpose or mixdown compressor application.

I've got a bag of 100 VR2N JFETs I picked up years ago that I could probably bin up in an afternoon - 1000 pieces would definitely exceed my curiousity level <grin>.

On another tac, what about two JFET compressors in series, each with a lower compression range (and therefore a lower gain signal recovery amp) for each stage, and a lower input resistor for each JFET voltage-controlled attenuator?

Thanks again for all the stimulating discussion!

mr coffee
 
mr coffee said:
Useful discussion for me - Thanks guys!

Most of the Application Notes I've read seem talk about using a signal level of up to  500 mv, across the JFET, albeit with 0.5% distortion and using 50% signal added into the JFET control voltage for distortion reduction - clearly a bit higher signal level across the JFET than the flagship models we seem to be primarily discussing here.
yes, depends on the application... guitar compressors do not need very high linearity.  Adding -6dB of AC drain signal to gate is very old trick that works.

The lowest distortion JFET limiter I recall was designed by Robert Cordell in his low distortion analyser article (published in audio magazine last century). Worth checking out for some cleverness. He used it in his low distortion sine wave oscillator AGC loop so not literally a comp/limiter. 
So perhaps a compressor that could tolerate less pristine distortion levels could have a much higher s/n ratio with perhaps fewer and less critically-matched JFETs? Even 1% distortion doesn't sound prohibitive if you are tracking guitar and not vocals. I'm not thinking of a general purpose or mixdown compressor application.
yup
I've got a bag of 100 VR2N JFETs I picked up years ago that I could probably bin up in an afternoon - 1000 pieces would definitely exceed my curiousity level <grin>.
google does not help me find a data sheet for VR2N ??
On another tac, what about two JFET compressors in series, each with a lower compression range (and therefore a lower gain signal recovery amp) for each stage, and a lower input resistor for each JFET voltage-controlled attenuator?
Tack? (sailing term).

When cascading gain stages the total noise will be dominated by the earlier stage since the later stage amplifiers the earlier stage noise too.
Thanks again for all the stimulating discussion!

mr coffee
Mature technology and well vetted.  Look up Cordell's AGC for best JFET practice (IMO), but best practice for a modern compressor is latest THAT VCA.

JR

PS: Back in the day I used JFET shunts in simple noise gates, but by definition a noise gate is only active when the audio signal is already lower (I could still hear the improvement from the -6dB gate drive trick. )
 
John,
Thanks for reply.
google does not help me find a data sheet for VR2N ??
My bad. VCR2N.
http://www.vishay.com/docs/70293/70293.pdf

Tack? (sailing term).
Yes - that's what I meant. Heard it used that way, just never learned how to spell it ::)

When cascading gain stages the total noise will be dominated by the earlier stage since the later stage amplifiers the earlier stage noise too.

I'm familiar with that concept about total noise being dominated by preceding stages, but I was wondering if that might still mean lower total noise in a cascaded  topology?  Please correct me if I'm wrong here, but if the first JFET attenuator and recovery amp stage has much lower noise (because the series resistor - maybe 3K ish - and the JFET resistance is much lower) and then that signal, including  the noise added by the first stage recovery amp, is attenuated by  the second series resistor - again 3K ish - and JFET resistance which also has a much lower resistance than the classic design, couldn't the overall aggregate signal/noise end up being lower? Maybe something other than a equal recovery gain in each stage?

Might there be additional virtues if the two cascaded stages had their own side chain with a fairly low gain reduction range (maybe 10 db ish apiece), in terms of smoothing gain recovery and "prettier" sounding abrupt gain reduction transients? Seems like I remember something about Dolby C doing something along that line somewhere in the deeper recesses of my mind ;D

Mature technology and well vetted.  Look up Cordell's AGC for best JFET practice (IMO), but best practice for a modern compressor is latest THAT VCA.

I searched for  the Cordell AGC, but not sure I found what you are referring to. What I came up with was an oscillator using a JFET to adjust the gain of the Wien Bridge oscillator in a variable audio sine wave oscillator circuit as an improvement over the old light bulb trick .  Looks like it handled maybe 6db maximum attenuation.

I have played around some with THAT VCAs, and have appreciated their wide range of attenuation and gain, and maybe I should just concentrate on developing a compressor circuit around them.  Best practice is best practice. 

I think what attracts me to the JFET as a voltage-controlled resistor in a voltage divider as a gain element is the impression that the JFET overload behavior might have a desirable character or sonic signature, ...which might or might not pan out.

Again, thanks to all for the stimulating discussion.

mr coffee
 
mr coffee said:
I'm familiar with that concept about total noise being dominated by preceding stages, but I was wondering if that might still mean lower total noise in a cascaded  topology?  Please correct me if I'm wrong here, but if the first JFET attenuator and recovery amp stage has much lower noise (because the series resistor - maybe 3K ish - and the JFET resistance is much lower) and then that signal, including  the noise added by the first stage recovery amp, is attenuated by  the second series resistor - again 3K ish - and JFET resistance which also has a much lower resistance than the classic design, couldn't the overall aggregate signal/noise end up being lower?
By replacing 27k with 3k AND reconfiguring the OSI for the recovery amp, you may gain a maximum of 9dB; cascading two stages will loose 3. So in theory, best case you would gain 6dB in S/N at the cost of having a limited (no pun...) range of GR. I would think in practice you may manage 4dB gain in S/N.

Maybe something other than a equal recovery gain in each stage?
Sure. You would not need the output amp for the first instance, just the recovery amp directly (with some attenuation) into the second FET.

Might there be additional virtues if the two cascaded stages had their own side chain with a fairly low gain reduction range (maybe 10 db ish apiece), in terms of smoothing gain recovery and "prettier" sounding abrupt gain reduction transients?
There are so many examples of people using several compressors in cascade for artistic reasons you wouldn't miss an opportunity to take advantage of it.

Seems like I remember something about Dolby C doing something along that line somewhere in the deeper recesses of my mind ;D
Dolby Labs are notorious for using multiple side-chains on one single gain cell. However, in Dolby C, they cascaded two instances of tweaked "B".

I searched for  the Cordell AGC, but not sure I found what you are referring to.
I did too.

What I came up with was an oscillator using a JFET to adjust the gain of the Wien Bridge oscillator in a variable audio sine wave oscillator circuit as an improvement over the old light bulb trick .  Looks like it handled maybe 6db maximum attenuation.
Yes; it did not use the half-signal on the gate; I believe the reason for good performance was that it was padded and buffered. You're right, the gain control range needs not be huge.

I have played around some with THAT VCAs, and have appreciated their wide range of attenuation and gain, and maybe I should just concentrate on developing a compressor circuit around them.  Best practice is best practice. 
You're right; they're so predictable it's not fun anymore  ;).

I think what attracts me to the JFET as a voltage-controlled resistor in a voltage divider as a gain element is the impression that the JFET overload behavior might have a desirable character or sonic signature, ...which might or might not pan out.
The sonic signature of the 1176 is pure serendipity. Now, you could probably achieve the same by combining a VCA compressor and a well-designed FET dirtyfier.
 
I am aware I may be displaying my ignorance here, but wouldn't paralleling a number of JFETs reduce the requirement for matching rather than increase it?

Nick Froome
 
pvision said:
I am aware I may be displaying my ignorance here, but wouldn't paralleling a number of JFETs reduce the requirement for matching rather than increase it?

Nick Froome
There would be a fraction of them doing all the work and the rest utterly useless. In fact, unless matched to incredibly tight tolerances, they would need individual adjustment of bias and control voltage.
 

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