mhelin

SDC FET amplifier without the input capacitor?
« on: January 02, 2019, 07:24:28 AM »
Screwable SDC capsules typically have only one connection available on a separate pin whereas the other comes from the ground connection via the screw threads making it difficult to supply the bias voltage to the backplate instead of to the diaphragm. Would it be possible to design the SDC head amp using a  p-channel JFET to get rid of the capacitor between the capsule and FET?  That way the grounded grid connection via 1G resistor could be made to the positive bias voltage instead of to the ground, and no input capacitor would be needed.The circuit would be similar than KM84 for an example but the input FET stage "mirrored".  Any problems with that, how about the p-channel JFET noise? Also the bias voltage filtering should not use any high value resistors, guess a single PNP capacitance multiplier type circuit would be fine (could be additionally zener regulated to ~40V).
« Last Edit: January 02, 2019, 08:15:01 AM by mhelin »
Mikko


moamps

Re: SDC FET amplifier without the input capacitor?
« Reply #1 on: January 02, 2019, 04:21:40 PM »
It could work, but it should be tested in practice for stability and noise. The problem, as you noted, would be finding an adequate p-ch  jfet (low noise, low Ciss, high Vdgs etc..). Maybe LSJ689 will do.

....Also the bias voltage filtering should not use any high value resistors, guess a single PNP capacitance multiplier type circuit would be fine (could be additionally zener regulated to ~40V)....
I don't follow you in this part.

Re: SDC FET amplifier without the input capacitor? New
« Reply #2 on: January 05, 2019, 09:14:36 AM »
Besides the usual problems of these one-FET + traffo schemes, this plan doesn't seem to have any additional ones to me.
The question is: what's the point of eliminating such an uncontroversial component (the coupling cap)? If you want the sound of the classics, why try to re-invent them?

For completeness I think those problems are high distortion mainly, I guess. Distortion stems from:
- Amplifier non-linearity. This could be significantly reduced  by eg. adopting a unity gain non-inverting topology. The modest gain obtained by the inverting configuration is hardly worth the excess distortion. This could then be improved again by adding an output stage of some kind to relieve the FET of cable driving duties.
- Excessive capsule loading. A nice simplified model of a capacitor mic consists of a so-called 'active capacitance', which changes dynamically with the sound pressure and 'passive capacitance' which does not. Loading the capsule with extra dead weight 'passive' capacitance not only attenuates the signal but causes the production of additional harmonic distortion. The Miller effect causes the input capacitance of the FET to be substantial in the inverting (common source) configuration. To make matters worse this capacitance is non-linear producing distortion products of its very own by interacting with the  (I'm assuming the two non-linearities don't serendipitously cancel each other, but I haven't checked that possibility). FET input capacitance can be all but eliminated by bootstrapping the drain terminal, increasing input level and reducing distortion dramatically.

Btw... For lower noise, using > 1 GOhm is just about the only game in town once you find a reasonable FET.
Best of luck!!

Edit:
A quick spice sim confirms that noise shouldn't be a problem with this plan. I'd presume that the p-channel noise model is pessimistic, but still noise is dominated by the resistor. Note that your plan reduces noise by almost 3 dB by eliminating one of the 1 GOhm resistors. You could achieve the same result (noise-wise) by doubling the two resistors in the original plan.
« Last Edit: January 06, 2019, 12:02:57 PM by VictorQ »


 

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