fripholm

ADC - word clock vs MCLK
« on: May 25, 2020, 08:38:37 AM »
I'm currently trying to wrap my head around the datasheets for the PCM4222 and its evaluation board PCM4222EVM.

On this board, MCLK is derived directly (through a buffer) from the external word clock input when the clock source is set to EXT.  When set to INT, two different VCOs at ~22 and ~24MHz are used which is much closer to what I would expect, frequency-wise.

When I scope the WC output of my audio interface, it's more or less a square wave with a frequency that matches the current sample rate, e.g. 44.1kHz. But according to the datasheet of the PCM4222, the MCLK is usually 128 or 256 times the sample rate which should be much higher in the MHz range (~5.6 or 11.2MHz in this case). LRCLK on the other hand matches the sample rate and as far as I can see there is a flip-flop (U21) that halves this to be used as SCKI.

So, how is it that this evaluation board works with an MCLK frequency that is much lower than needed? What am I missing?


abbey road d enfer

Re: ADC - word clock vs MCLK
« Reply #1 on: May 25, 2020, 02:24:06 PM »
I'm currently trying to wrap my head around the datasheets for the PCM4222 and its evaluation board PCM4222EVM.

On this board, MCLK is derived directly (through a buffer) from the external word clock input when the clock source is set to EXT.  When set to INT, two different VCOs at ~22 and ~24MHz are used which is much closer to what I would expect, frequency-wise.

When I scope the WC output of my audio interface, it's more or less a square wave with a frequency that matches the current sample rate, e.g. 44.1kHz. But according to the datasheet of the PCM4222, the MCLK is usually 128 or 256 times the sample rate which should be much higher in the MHz range (~5.6 or 11.2MHz in this case). LRCLK on the other hand matches the sample rate and as far as I can see there is a flip-flop (U21) that halves this to be used as SCKI.

So, how is it that this evaluation board works with an MCLK frequency that is much lower than needed? What am I missing?
The master Clock input is not designed to receive WC; it needs a 4 to 24MHz clock, as explained in table 4 of teh data sheet.
Who's right or wrong is irrelevant. What matters is what's right or wrong.
Star ground is for electricians.

fripholm

Re: ADC - word clock vs MCLK
« Reply #2 on: May 25, 2020, 03:24:51 PM »
Aahh, I see   :-[

I guess, I saw 'BNC connector' mentioned and thought, this has to be for word clock - as this connector type is (also) used by WC...

If I wanted to use WC as sync master, this needs to be multiplied somehow, right? PLL? Any other ways?

abbey road d enfer

Re: ADC - word clock vs MCLK
« Reply #3 on: May 25, 2020, 02:29:29 PM »
Aahh, I see   :-[

I guess, I saw 'BNC connector' mentioned and thought, this has to be for word clock - as this connector type is (also) used by WC...

If I wanted to use WC as sync master, this needs to be multiplied somehow, right? PLL?
that's usually how it's done.
Who's right or wrong is irrelevant. What matters is what's right or wrong.
Star ground is for electricians.


 

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