abbey road d enfer

Re: AES/EBU input pulse transformer capacitors?
« Reply #20 on: November 05, 2020, 04:02:58 PM »
Yes the receiver can recover and correct for some of it.  But that s an unknown and dependent on receiver design.  If you prefer it be stated that the eye opening is proportional to error rate given the receiver takes no corrective action, I'm ok with that. Or perhaps potential error rate is a better description.
But the receiver, being digital, always has a corrective action. Within quite large limits, it is impervious to jitter.
Who's right or wrong is irrelevant. What matters is what's right or wrong.
Star ground is for electricians.


john12ax7

Re: AES/EBU input pulse transformer capacitors?
« Reply #21 on: November 05, 2020, 04:06:19 PM »
Thanks, that's just the trafo and the caps... So the idea is to test the trafo without any load but the scope?

Yes,  basically an eval board to isolate the performance of the transformer. The other thing would be to also have a thru line on the board,  to test the integrity of the pcb traces, and then you can use that data to subtract out the board influence. That's kind of the industry standard way of doing things.  Often times manufacturers will do this for you.

Bear in mind that I used to do a lot of device characterization at frequencies where every little thing matters,  so I might be unduly influenced by that. It might be simpler to just build the actual converter circuit and see if you notice a difference.

john12ax7

Re: AES/EBU input pulse transformer capacitors?
« Reply #22 on: November 05, 2020, 04:14:20 PM »
But the receiver, being digital, always has a corrective action. Within quite large limits, it is impervious to jitter.

That hasn't been my experience in non-audio applications.  In audio specifically I've heard differences due to jitter,  and am of the opinion that the amount and frequency profile of jitter matters,  it's not just an above or below threshold issue.  I do realize not everyone shares that opinion.

living sounds

Re: AES/EBU input pulse transformer capacitors?
« Reply #23 on: November 06, 2020, 05:38:00 PM »
So you mean I should test what happens without the transformer? I never thought about that, but it is indeed not really necessary here. There source is transformer balanced and the receiver chip (MAX3280E) has A-B inputs (no ground connection).

Interestingly, the DA side uses the exact same transformers and has the same caps on the outputs. As have the analog inputs and outputs. That's why I'm starting to think it was just as a safety precaution against RF on all fronts (and backs).

The receiver chip doesn't remove any jitter and there is no traditional PLL: "The DAC uses a low jitter digital controlled oscillator (SiLabs si570), data is sent though a short FIFO and the FPGA and uC work together to measure incoming bitrate and adjust clock as needed, basically a digital PLL with very fast lock and very slow filtering."

In theory it should put out a perfect 0.8 ps clock signal to the DAC, but there are all kinds of differences audible depending on the source. I can point you to a very long thread about that converter if you are interested, other people are hearing these differences, too.

john12ax7

Re: AES/EBU input pulse transformer capacitors?
« Reply #24 on: November 06, 2020, 06:56:00 PM »
I meant you could build your circuit with the transformer and then test caps / no caps in actual use.

Typical RF protection filters out of band signals. The 100pF caps will be affecting the in band AES signal as well given the frequency and impedance.

You can send the link,  I'll check out out.

abbey road d enfer

Re: AES/EBU input pulse transformer capacitors?
« Reply #25 on: November 07, 2020, 11:10:21 AM »
The receiver chip doesn't remove any jitter and there is no traditional PLL: "The DAC uses a low jitter digital controlled oscillator (SiLabs si570), data is sent though a short FIFO and the FPGA and uC work together to measure incoming bitrate and adjust clock as needed, basically a digital PLL with very fast lock and very slow filtering."
I didn't say that the PLL was "traditional". There is a PLL, and as such does reduce jitter.

Quote
In theory it should put out a perfect 0.8 ps clock signal to the DAC, but there are all kinds of differences audible depending on the source. I can point you to a very long thread about that converter if you are interested, other people are hearing these differences, too.
I'm modestly interested. Is there a definitive conclusion that the differences are jitter-related?
I've read a lot about this subject and experiments that have been done. It almost always boiled down to the PLL, not the analog transmission of the digital signal. Within limits, of course.
Who's right or wrong is irrelevant. What matters is what's right or wrong.
Star ground is for electricians.


 

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