Discrete JFET-NPN Cascode Input OPAMP

I am trying to drag myself (kicking and screaming) into the mid 20th century. I know little about transistors but have been learning as I go via this forum.

Several of you have come up with interesting designs for OPAMPs of your own and many classic designs have been examined, much to the benifit of folks like me.

Now, I have been kicking around a discrete design for an OPAMP using a JFET-NPN cascode input. Nothing in this design is revolutionary as I simply stole outright work others have done. So far I have only worked on a simulator to try to get a feel (within the SPICE model parameters) for how things would work on a breadboard.

I would like to solicit your comments, criticism and help in giving this little circuit a going over. I have tried to keep it simple but I am hoping to get at least descent performance with low noise. Since I am an avowed idiot, I await your input.

The schematic follows: http://users.adelphia.net/~thomasholley/JFET-NPN Cascode Input OPAMP.gif

I am hoping to foster a dialoge so that I, and maybe others can learn. I am little concerned that my circuit gets deconstructed.

Thanks, as always.

Looks good, but please tell us about your design goals. What do you hope to accomplish with this opamp? What would be the primary use or application? No single opamp fits all applications contrary to the notion of the "generic opamp."

My first impression is that it is a rather high gain amplifier (beta is over 10,000 in the VAS) that is not going to be stable at low gains especially with the smallish 33p capacitor shown in the VAS loop. Then again I do not know if that is a requirement for you or not.

Expecially Q7 and perhaps Q8 might have a hard time dealing with the 24V rails indicated.

Do D3 and D4 do anything?

Depending on how fussy one gets about sharing voltage references R9, D7 and D8 may be redundant. If you care leave them there.

Tamas

Tamas, Thanks for looking at this. As for design goals, I really don't have anything specific except to try to figure out how these things work. You have done so much work on discrete OPAMPs that I am very pleased for your comments. Since I am looking at a cascode input, low noise and high gain, I think maybe this could be most suited for applications like microphone preamp duty. But, I am really wanting to garner discussion more than anything else.

D3 and D4 are there because someome else had them there and I coppied. I think they are probably not relevant though. I'll toss them and see what happens.

I am really not clear as to what exactly the 33p capicator does. Does it have most effect on slew rate? I will go up in value to 150p like in a 990.

Since I really don't know transistors worth a damn, what would you suggest for Q7, Q8. The 2n44xx seem to be used frequently but as you intimate, they are only 40V devices and a bit smallish in this capacity.

Since most designs I have seen use seperate biasing for the current sinks, I figured sharing the diodes and rail resistors may cause unwanted interaction. Thinking about it though, these parts only set the base voltage, and in both cases they are the same. I think a coulpe of more parts may vanish.

After some preliminary going over, I will order parts and breadboard the circuit so we can see what developes.

A question I have about biasing the bases of the MPSA18. I needed to have a largish pullup resistor (100k or more) to the positive rail to get the bias stable. I played around with adding a capicator (C4) to see if stability was better (simulated) and found this gave a slight boost to the low end, depending on the resistor/capacitor combination of course. What are your thoughts on a capacitor here?

Again, Thanks.

...

Even on simulation, the capacitor on the base of the BJT looks a little hinkey, thus my question on it's use. I think I will omit it and save a few cents. For biasing these bases, is a pullup resistor sufficient or is a voltage divider more appropriate?

Douglas Self explains a lot of this really well.
I would recommend buying his book. It is an excellent work.
Here is a good start to learn about distortion mechanisms.
http://www.dself.dsl.pipex.com/ampins/dipa/dipa.htm
It kind of drives his entire design process.

[quote author="thomasholley"]
I am really not clear as to what exactly the 33p capicator does. Does it have most effect on slew rate? I will go up in value to 150p like in a 990.
[/quote]
That capacitor creates a local feedback path. Q7 is just an emitter follower, but it enhances the gain of Q8 significantly. All this gain makes the amp unstable so feedback is applied through that C3 capacitor. The capacitor has to be charged for each cycle and that limits the slew rate. The capacitor is charged by the current that flows through Q5, Q3 and J1B so the slew rate is effected by:
a. The current in the long tail pair (LTP)
b. The capacitor C3

[quote author="thomasholley"]
Since I really don't know transistors worth a damn, what would you suggest for Q7, Q8. The 2n44xx seem to be used frequently but as you intimate, they are only 40V devices and a bit smallish in this capacity.
[/quote]
Transistors rarely take kindly to their Vce ratings exceeded. For simplicity and safety you can look at their Vce rating and make sure they can take at least 20% more than your rail-rail figure.


[quote author="thomasholley"]
Since most designs I have seen use seperate biasing for the current sinks, I figured sharing the diodes and rail resistors may cause unwanted interaction.
[/quote]
Good thinking. If you have enough real-estate you should stay with them.


[quote author="thomasholley"]
After some preliminary going over, I will order parts and breadboard the circuit so we can see what developes.
[/quote]
IMHO, that is the best ways to learn.


[quote author="thomasholley"]
A question I have about biasing the bases of the MPSA18. I needed to have a largish pullup resistor (100k or more) to the positive rail to get the bias stable.
[/quote]
As John mentioned using two resistors to bias those transistors (a resistor to + rail and the other to that current source, collector of Q6) may yield more predictable results.

...

Thanks again for your thoughts. I have looked at Douglas Self's site a few times and always find it enlightening. I will see about his book.

For the VAS transistors, what about BC556? They are listed at 65V and are catagorized as low noise and are cheap and available.

For an input FET I noticed Linear Systems has an "ultra low noise dual matched FET" LS843. Has anyone tried one of these. I did a brief search but couldn't find them for sale so they are not widely available and may be expensive. I have thought of getting some LSK170 FETs and trying to match them or use a small trimmer in the source junction if necessary, like Fred Fossell did in his class a design. I think I can get a couple of the 2SK389s for $3 or$4 though, if that is what the OPAMP ends up needing.

I will work on the divider for the MPSA18 bases and see what turns up.

I also don't think the current source biasing will suffer with a single pair of diodes. I will certainly test it and see.

> a JFET-NPN cascode input.

OK, why? Every time I feel the need to cascode, I lay down until a better plan comes to mind.

What benefits do you hope to get?

Usually, you want to keep the voltage across the input device low or stable, to reduce leakage, Miller effect, or avoid breakdown.

What IS the voltage across your FETs? Ignoring the capacitor, looks like (V+)-(Ib*510K). What is Ib, the Q2 Q3 base current? NOT what lies-to-8-places SPICE says, what is it in real life, to cocktail-napkin precision? Q6 is sending up 5mA. And altho SPICE may say the A18 Beta is 234.56, the datasheet says a wide range, something like 100-300 (too hot to look it up). So the Q2 Q3 sum base current is 5mA/100 to 5mA/300, or 0.05mA to 0.017mA. Times 510K, 25V to 8V. Down from the positive rail!!! NOT up from the FET sources or gates!!!

If the R5 voltage is 25V, and the rail voltage is 24V, the FETs can't even pass current for inputs near ground. Even if it is less, it limits how positive the inputs can swing.

If the R5 voltage is 8V and the inputs are near ground, the FETs see 16V which may be enough to increase leakage.

If the input voltage swings up and down (follower instead of inverter) we get full Miller effect.

And a cascode top-stage bias should be SOLID. If it isn't, much advantage is lost and strange things happen.

In short: the cascode is not doing anything good, and in real-life can cause non-operation.

C4 bootstraps the Q2 Q3 bases, reduces Miller and variation of leakage. BUT you have gone to some trouble with Q6 to get a very-high impedance in the long-tail, to improve CMRR. And then you tie the 510K resistor to it, significantly reducing the node impedance.

How did you arrive at C4=100nF? What is the impedance here? Frankly, I don't know. Whatever it is, I would expect some low-frequency anomaly as the Miller capacitance, FET Vds, long-tail impedance, and other parameters change from bootstrapped to free.

Decide what voltage you want where. You probably want about 7V across the FETs, drain to source. You do NOT want to load the source node. So you need a buffer to sense the source node, follow its voltage, jack it up about 7V higher, and feed the Q2 Q3 bases from that.

The function of C3 is critical, and that value does not look right for that input stage.

As for the rest of it.... it looks familiar.

Read National Semiconductor paper AN-A: The Monolithic Operational Amplifier: A Tutorial Study

The pages on thermal feedback are of little importance in discrete design.

The small signal frequency response and slew-rate sections are critical to designing a general-purpose feedback amplifier. Their way is not the only way, but it is sweet for its simplicity.

The FET-input section seems relevant to your scheme, but note that their skinny FETs are not much like the fat 170.

Cascode bootstrapping is illustrated in the LM108 datasheet. Page 3, Q28 and Q27 buffer the Q29 longtail and Q1 Q2 input emitters to drive the bases of Q5 Q6 cascodes, keeping Q1 Q2 collector-emitter voltage steady at ~0.6V. This could be modified for a higher voltage to keep FETs alive.

Thanks again for your comments and criticism. I have made some updates to the schematic:http://users.adelphia.net/~thomasholley/JFET-NPN Cascode Input OPAMP 2.gif

I took out the capacitor I had at the base of the input transistors. Now that that stupidity is behind me, I did a simple divider for bias, tied to ground so it shouldn't affect the impedence of the current sink at the input amp.

The way it stands now, I have about 10V across the MPSA18 and 11V across the FET. About 2.8mA in each diff half. The first VAS transistor draws about 900uA and the second transistor draws about 7mA. This seems to be OK in my lyingassed simulator. I appreciate your comments.

As for what I expect from a cascode input, well, I hope it may give a bit better noise performance, increased output impedence and reduced miller capacitance. I could be just full of crap though. The choice of JFET/BJT came from reading discussions here. I hope to see if the input stage can benefit from the high input impedence of the fet while still getting the benefit of the BJT gain. I do, however, feel a nap comming on.

Like I said at the outset, this is not a new design, but cobbled together pieces from others, and in some respects, all too familiar...to most of you. Though redundancies exist in my effort, I am not alone in the knowledge gained when experienced people take apart the circuit. I know this may get old sometimes, and in some instances repetitative, but thanks for continuing to teach us numbskulls.

I now better understand the critical nature C3. I just don't know how to calculate the proper value. From a quick look at the National tutorial a rough estimation for slew rate is tail current/Feedback capacitor. It becomes more involved when considering pole response I am sure. I'll keep reading.

I continue to welcome your comments. Thanks.

> I have about 10V across the MPSA18 and 11V across the FET

Only when the inputs are near zero volts.

That will be true only for inverter use (with one input grounded) or for very high-gain followers. While many traditional opamps had low limits on input swing, the 741 taught us to expect the output to swing well past +/-10V (on +/-15V supply) and for the inputs to have the same swing (so voltage followers were possible).

So what happens when your inputs swing? Since the BJT bases and emitters are fixed, the Miller effect is still there. If inputs swing to +10V, the JFETs lose drain-source bias and quit; we might want more considering +/-24V rails.

That 500K/1Meg bias string looks awful high impedance for bases of BJTs flowing ~5mA total. What is your bias-string current, what is your sum base current? Will small variations of Beta cause large variations in base voltage?

> what I expect from a cascode input, well, I hope it may give a bit better noise performance, increased output impedence and reduced miller capacitance

Miller is still here.

Why would it improve noise? Yes, bad old BJTs had noise-rise at high collector voltages, and absurd voltages are still a poor idea in any device. And high voltage with plenty of current leads to heat, and noise is proportional to temperature (but absolute temperature: reasonably-hot parts have only slight noise rise). But with clean devices at reasonable voltage and heat, noise effects are small. There seems little wrong with the JE-990, even though it runs 22V and more across the input devices.

Output impedance? When you work out the frequency compensation to be stable at low gains, you will probably have a very low node impedance.

> I just don't know how to calculate the proper value.

Find ALL your high-frequency roll-offs. Some are high enough to be neglected. Using Self's topology and notation, the key poles are the node between the input collectors and the VAS, the VAS output, and the output emitter followers. In 741-era chips, the PNP was bad to begin with and really punked-out at 1MHz. The pole-split compensation combines the first two critical nodes into one 6dB/oct 90 degree rolloff. This has to reduce gain below unity before the output stage craps-out, around 1MHz. That means that the compensation cap reactance equals the input stage emitter resistance at <1MHz. If we look in a 741/301, we have Cc about 30pFd, input emitters work at ~10uA so are about 3K each, 6K total. 30pFd = 6K at 880KHz. If the finished amplifier will never work at gain of less than 10, we can aim for the compensation to give gain of less than 10 at <1MHz, and indeed for this condition the 301 calls for Cc to be 3pFd.

With the best audio discrete outputs, you can get the output stage to hold together to 10mHz (though it isn't inevitably that good). Before the isolated IC processes with good PNPs, that was the key reason to use discrete: about 10X more usable bandwidth, or 10X more feedback in the audio band.

That's much better

...

Thanks for the look at this. While biasing the bases with a voltage dvider, I only considered getting a certain voltage, and neglected current altogether(only 2/3 Ohms Law). What an idiot! Being blind, deaf and stupid is sometimes a hindeance, that is why I try this on paper first before I spend my pennies on parts to fry.

Cascodes are touted, on paper at least, as a most wonderful thing indeed. But I don't see them used that often in transistor circuits (again, I have very limited exposure here). There is probably a reason for this other than cost. I do know that cascode is useful in some applications in tube circuitry and am trying to extrapolate to transistor. I realise there are plenty of very good discrete OPAMPs floating around. I certainly don't think any design I could come up with would best most, maybe any of these. I am just hoping to learn from your help, stimulate an intelectual discourse and maybe come out the other end with an at least useful topology. We shall see.The worst that could happen is I fry a few parts, get shamed in the forum, become despondent, homeless and finally end it all by jumping from the bridge.

I am not giving up yet. I will work some more on my paper model. By the way, an important note, I am using Tamas' testing topology from his "B7 Discrete Operational Amplifier" paper to test in simulation, and will use it on the breadboard. I will post it in my next update. The paper is in the Meta for those who need it.

Here is a link to an updated schematic: http://users.adelphia.net/~thomasholley/JFET-NPN Cascode Input OPAMP 3.gif

And the testing circuit simulation from Tamas' paper: http://users.adelphia.net/~thomasholley/Test Circuit.gif

I hope this is a little more reasonable, progress vice regress. I still must work on the feedback cap determination so I can get a reasonable value (ballpark) before breadboarding.

Thanks.

How about the VAS? Should it be cascoded as well?
I am curious about the difference in sound myself.

I could just do an experiment and cascose the works. Seriously though, It should not be too much of a problem to do the VAS and see if it makes a difference.

Hey, that's unfair! Two weeks on holiday, and what do I find when I get back? Someone already tried the opamp I had in my mind for some weeks! :grin:

As PRR said, you want to reference the cascode bias to the R1/R2-common node and not to ground for several reasons. Run a resistor between this node and Q2/Q3 bases and feed it from above with a current source.

Check this Apex datasheet (pa09u.pdf), if I was not clear enough.

Cascoding the VAS is interesting, but I doubt that it will sound or measure that different. Remember that you need a emitter follower befor the output stage or the VAS will distort due to loading, at least when the output leaves class A.

Samuel

Samuel
Thanks alot for this advice. I have ordered some parts and will breadboard circuits this week and report back on my findings.