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What a thread! After reading through this and related threads, I think I've pieced together the consensus circuit. That is:

  • JFET input circuit with LSK389
  • Emitter follower output for low output z
  • Vcc for JFETs regulated to 15v via zener, rather than cascode

I haven't built this up yet. I basically mashed up the FEThead/Alctron, etc. circuit with the zener regulator and emitter follower from Schoeps/Helmke. But thought I'd leave it hear for anyone like me reading through this thread and trying to piece together a circuit from all the recommendations.
 

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abbey road d enfer said:
The zener is not needed. 15V is not essential.
And as it is, it's a significant source of noise.

Gotcha, thanks. And thanks for pointing out the drain resistors, Volker.

To clarify, you're saying the distortion from the zener is worse than the noise from the drain voltage exceeding 15v?

In that case it seems like the ideal would be the cascode followed by the emitter followers, no?
 
Peterson Goodwyn said:
To clarify, you're saying the distortion from the zener is worse than the noise from the drain voltage exceeding 15v?
Zener does not generate distortion, it generates noise.
What's wrong with a little more than 15V? Anyway, you adjust the voltage by adjusting the base resistors of the PNP's.

In that case it seems like the ideal would be the cascode followed by the emitter followers, no?
Cascode here is a waste of FET's.
 
I don't believe it's posted in the thread, but based on the comments above I assume it's like this. I haven't dialed in resistor values. Will post a schematic once I've settled on them and tested it.
 

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Peterson Goodwyn said:
I don't believe it's posted in the thread, but based on the comments above I assume it's like this. I haven't dialed in resistor values. Will post a schematic once I've settled on them and tested it.

I think Abbey posted it in some thread...
As fas as I remember theres at least 3 threads on this subject, all of them have relevant info, just do a search and you will find them, I dont remember the names at the moment
 
Peterson Goodwyn said:
I don't believe it's posted in the thread, but based on the comments above I assume it's like this. I haven't dialed in resistor values. Will post a schematic once I've settled on them and tested it.
I don't think thats it as there appears to be two AC coupling caps on the PCB.
 
Whoops said:
I think Abbey posted it in some thread...
As fas as I remember theres at least 3 threads on this subject, all of them have relevant info, just do a search and you will find them, I dont remember the names at the moment
I have been following the threads for awhile. I have looked again, but cannot find it.
 
Other threads relevant to this subject:

https://groupdiy.com/index.php?topic=75923.0

https://groupdiy.com/index.php?topic=72896.0

https://groupdiy.com/index.php?topic=74016.msg937308#msg937308

https://groupdiy.com/index.php?topic=50924.0

https://groupdiy.com/index.php?topic=49391.0

https://groupdiy.com/index.php?topic=46930.0

https://groupdiy.com/index.php?topic=74048.msg937613#msg937613
 
Peterson Goodwyn said:
I don't believe it's posted in the thread, but based on the comments above I assume it's like this. I haven't dialed in resistor values. Will post a schematic once I've settled on them and tested it.
I'm too lazy to recreate the .asc file. Can you post it?
What gain do you measure?
 
abbey road d enfer said:
I'm too lazy to recreate the .asc file. Can you post it?
What gain do you measure?

I'm getting 25dB gain, 0.015 THD with the Sbias and Cbias values shown here. Not too bad. .asc is here: http://DIYRE.quickconnect.to/d/f/603326970513636281

abbey road d enfer said:

Thanks. I notice you used 220n coupling caps, then biased the drains via 1k resistors collectors. Can you explain the benefit of that vs just letting V+ pass through the PNPs as I did?
 

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Peterson Goodwyn said:
I'm getting 25dB gain, 0.015 THD with the Sbias and Cbias values shown here.
At what level?

  I notice you used 220n coupling caps, then biased the drains via 1k resistors collectors. Can you explain the benefit of that vs just letting V+ pass through the PNPs as I did?
The FET's operate at a much higher current, which is good for noise, and the gain is almost independant from the load.
 
Peterson Goodwyn said:
I'm getting 25dB gain, 0.015 THD with the Sbias and Cbias values shown here. Not too bad. .asc is here: http://DIYRE.quickconnect.to/d/f/603326970513636281
The PNP's in your schemo are doing nothing. They are constantly saturated at 23mV Vce.
The FET's are doing the heavy lifting.
I have built the very simpleversion, similar to the original version of Fethead, before they used the cascode arrangement.
The main problem is that the FET's are in risk of being submitted to the full 48V and the output impedance is high (current source), which makes the gain dependant on teh load, and present a high Z source to teh peramp, no good for noise.
 
Awesome, thanks. Now I see how I had the biasing all messed up. I played around with this in LT Spice today and these values give 25dB gain and ok distortion (<0.1%THD) at -45dBu input.

I drew up a little PCB: https://oshpark.com/shared_projects/w3wEWLH9

Again, I haven't built this yet so use at your own risk.
 

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