ADAT in/out interface

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Dimitree

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Jul 26, 2011
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32
hello everyone,
I'm trying to design an interface with ADAT in/out and 8x ADC channels, and 8x DAC channels, that I'd like to use with RME-Digiface USB (4x ADAT in, 4x ADAT out).

this is the first sketch (digital side only, no analog) that I drawn before starting with the actual schematic, since I'm still trying to understand if the whole system could work..

Basically, it would be built around the AL1401 and AL1402 ADAT encoder/decoder. There would be 4x PCM4222 adc and 4x PCM1794A dac.
Every chip would be configured as slave, the master clock would be provided by either an external source (Word Clock, fS), an internal pair of crystals (depending on the sample rate), or from the ADAT IN stream (via AL1402). The LR clock and the Bit Clock would be divided by the master clock. The two ADAT chips only need Word clock when used as slave, so LRCLK and BCLK would only be provided to the converters.
It would only work with 44.1K and 48K sample rates.

The only user selectable controls would be the master clock source and the bit resolution (16 or 24).

What do you think?

thank you! :)
interface_v1.png
 
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Dimitree

Active member
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Jul 26, 2011
Messages
32
so I started drawing the clock section,
after many mistakes I come up with this, I hope there are no more mistakes.

Basically a 4-way switch to enable/disable the tri-state buffers placed after each clock source.
I discarded the idea to use the CS2300 PLL chip because that chip cannot be easily found anymore, and since I don't want to implement a proper PLL, I just decided to use a 256fS external clock input instead of a standard Word clock input, afterall I need this feature only to sync more clone of this unit, I don't have any other digital equipment that I have to sync to this, so who cares about word clock..

if you're wondering why there is a WCLK and a WCLK_5V, it's because ADAT chip only supports 5V while the DAC and ADC only 3.3V

I'm wondering if I should place a buffer between the two oscillators and the following flip-flop,
once I understand this, I will decide whether to use a single 74LVC125 or multiple 74LVC1G125 as shown at the moment, but probably I will decide that once I'm going to do the layout.

what do you think, how is going so far?

clock.png
 

Andy Peters

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Oct 29, 2007
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Sunny Tucson
Wow, I am suddenly getting notifications for GroupDIY! Weird.

If I was to do this, I'd blow off the AL1401 and 1402 and do all of the work in a small FPGA, like a Lattice MachXO2 or an Intel Cyclone 10. That eliminates finding the oddball Alesis parts and their 5 V supply. MachXO2 can run on a single 3.3 V supply. I don't remember if Cyclone needs a lower core voltage.

ADAT format is fairly trivial to manage, and going with an FPGA you can easily implement SMUX to get half the channels at 96 kHz sampling. So too is I2S for the converter interface. You can use TDM for the ADC interface if you like.

Both oscillators come into the FPGA which is where the selection is performed, and the FPGA divides down the selected master clock to get the bit shift clock and the LRCLK.

You might need a way to configure your ADCs and DACs to use the desired data formats, but that's a simple state machine in the FPGA. Managing buttons and LEDs in the FPGA is easy, too.

Good luck, have fun.
 

Dimitree

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Jul 26, 2011
Messages
32
Thanks! I actually thought about ditching the two AL chips, obviously those chips are the bottleneck of the whole system from a performance point of view, but I really don’t have time or will to learn about FPGAs. I’m a software developer and I am trying to avoid programming as much as possible when I’m not at work :)
 
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mhelin

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Mar 12, 2005
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546
Location
Tampere, Finland
There are also replacement parts V1401 and V1402 available from Coolaudio (sold here: Cabintech Global LLC). Not FPGA but something else the XMOS XCORE chips which are used in 90% of USB audio interfaces have also ADAT libraries for ADAT support available including SMUX.

Regarding the clock generation you could also use on of the (A/D) converters in master mode to generate the other clocks (WCLK, BCLK) from the MCLK.
 

Dimitree

Active member
Joined
Jul 26, 2011
Messages
32
Regarding the clock generation you could also use on of the (A/D) converters in master mode to generate the other clocks (WCLK, BCLK) from the MCLK.
that was the original idea, but then I noticed that the PCM4222 outputs a 128fS BCLK in Master Mode, and even if the ADAT chips only need WCLK, I guess the ADC would output the data twice as fast as what the ADAT chips would expect. In Slave mode the PCM4222 can handle 64fS as BCLK. That’s why I’m using all the chips in Slave mode and generate BCLK from MCLK
 

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