ADAT in/out interface

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Dimitree

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hello everyone,
I'm trying to design an interface with ADAT in/out and 8x ADC channels, and 8x DAC channels, that I'd like to use with RME-Digiface USB (4x ADAT in, 4x ADAT out).

this is the first sketch (digital side only, no analog) that I drawn before starting with the actual schematic, since I'm still trying to understand if the whole system could work..

Basically, it would be built around the AL1401 and AL1402 ADAT encoder/decoder. There would be 4x PCM4222 adc and 4x PCM1794A dac.
Every chip would be configured as slave, the master clock would be provided by either an external source (Word Clock, fS), an internal pair of crystals (depending on the sample rate), or from the ADAT IN stream (via AL1402). The LR clock and the Bit Clock would be divided by the master clock. The two ADAT chips only need Word clock when used as slave, so LRCLK and BCLK would only be provided to the converters.
It would only work with 44.1K and 48K sample rates.

The only user selectable controls would be the master clock source and the bit resolution (16 or 24).

What do you think?

thank you! :)
interface_v1.png
 
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Dimitree

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so I started drawing the clock section,
after many mistakes I come up with this, I hope there are no more mistakes.

Basically a 4-way switch to enable/disable the tri-state buffers placed after each clock source.
I discarded the idea to use the CS2300 PLL chip because that chip cannot be easily found anymore, and since I don't want to implement a proper PLL, I just decided to use a 256fS external clock input instead of a standard Word clock input, afterall I need this feature only to sync more clone of this unit, I don't have any other digital equipment that I have to sync to this, so who cares about word clock..

if you're wondering why there is a WCLK and a WCLK_5V, it's because ADAT chip only supports 5V while the DAC and ADC only 3.3V

I'm wondering if I should place a buffer between the two oscillators and the following flip-flop,
once I understand this, I will decide whether to use a single 74LVC125 or multiple 74LVC1G125 as shown at the moment, but probably I will decide that once I'm going to do the layout.

what do you think, how is going so far?

clock.png
 

Andy Peters

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Wow, I am suddenly getting notifications for GroupDIY! Weird.

If I was to do this, I'd blow off the AL1401 and 1402 and do all of the work in a small FPGA, like a Lattice MachXO2 or an Intel Cyclone 10. That eliminates finding the oddball Alesis parts and their 5 V supply. MachXO2 can run on a single 3.3 V supply. I don't remember if Cyclone needs a lower core voltage.

ADAT format is fairly trivial to manage, and going with an FPGA you can easily implement SMUX to get half the channels at 96 kHz sampling. So too is I2S for the converter interface. You can use TDM for the ADC interface if you like.

Both oscillators come into the FPGA which is where the selection is performed, and the FPGA divides down the selected master clock to get the bit shift clock and the LRCLK.

You might need a way to configure your ADCs and DACs to use the desired data formats, but that's a simple state machine in the FPGA. Managing buttons and LEDs in the FPGA is easy, too.

Good luck, have fun.
 

Dimitree

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Thanks! I actually thought about ditching the two AL chips, obviously those chips are the bottleneck of the whole system from a performance point of view, but I really don’t have time or will to learn about FPGAs. I’m a software developer and I am trying to avoid programming as much as possible when I’m not at work :)
 
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mhelin

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There are also replacement parts V1401 and V1402 available from Coolaudio (sold here: Cabintech Global LLC). Not FPGA but something else the XMOS XCORE chips which are used in 90% of USB audio interfaces have also ADAT libraries for ADAT support available including SMUX.

Regarding the clock generation you could also use on of the (A/D) converters in master mode to generate the other clocks (WCLK, BCLK) from the MCLK.
 

Dimitree

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Regarding the clock generation you could also use on of the (A/D) converters in master mode to generate the other clocks (WCLK, BCLK) from the MCLK.
that was the original idea, but then I noticed that the PCM4222 outputs a 128fS BCLK in Master Mode, and even if the ADAT chips only need WCLK, I guess the ADC would output the data twice as fast as what the ADAT chips would expect. In Slave mode the PCM4222 can handle 64fS as BCLK. That’s why I’m using all the chips in Slave mode and generate BCLK from MCLK
 

Dimitree

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I've been trying to finish the schematic, and this is what I came up with.
Every part of the schematic is based on the datasheets and eval.boards schematics.

Just for the records, there are still some things I need to understand before committing the schematic to a PCB prototype, and those are:
1) analog input and output levels. I followed the datasheet/eval.boards suggestions for both ADC and DAC, but those may not be the optimal levels for such application. Also I went for single-ended output on the DAC, but differential input for the ADC.
2) Somewhere online I read that there are some issue with the PCM4222 on power up, so that the chip needs a reset, but I need to investigate that.
3) check again the phase of all the clock signals. Probably they are fine, since the ADAT chips only need WCLK, but I remember that once I read that one of the two ADAT chips had opposite clock logic than usual.
4) I need to put some buffers on the clock lines, but that will be done when making the PCB layout

DAC:
dac.png


ADC:
adc.png



ADAT:
ADAT.png
 

ccaudle

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Basically a 4-way switch to enable/disable the tri-state buffers placed after each clock source.

Careful with the stubs when you lay that out. Do you have a scope with enough bandwidth and resolution to show if you are getting reflections on the clock edges?
 

ccaudle

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What is the intention of the 33pF capacitor between output and pin 5 of the OPA134? Pin 5 is no-connect on OPA134.

Since you are using TRS connectors on the DAC output, you should make an impedance balanced output by connecting the equivalent impedance from R to reference close to the output amp, that way you can use it as a balanced or SE output with no problems. For power line frequencies just connecting a 100 Ohm resistor to that pin to match R41 and R42 should be pretty close.

Using op-amps configured as diff-amps on the input will not have very good real world CMRR. See many articles written by Bill Whitlock and Jim Brown, as well as app notes from That Corp. for background. You don't have to go with the full InGenius designs from That, but at least using an instrumentation amp configuration would give much better CMRR if that is a concern.
Filtering on the input for EMI/RFI/ESD is also recommended
 

Dimitree

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Careful with the stubs when you lay that out. Do you have a scope with enough bandwidth and resolution to show if you are getting reflections on the clock edges?
thanks for the tip! I don't fully understand the issue here, you mean that it would be difficult to design a PCB for that section?
 

Dimitree

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What is the intention of the 33pF capacitor between output and pin 5 of the OPA134? Pin 5 is no-connect on OPA134.

Since you are using TRS connectors on the DAC output, you should make an impedance balanced output by connecting the equivalent impedance from R to reference close to the output amp, that way you can use it as a balanced or SE output with no problems. For power line frequencies just connecting a 100 Ohm resistor to that pin to match R41 and R42 should be pretty close.

Using op-amps configured as diff-amps on the input will not have very good real world CMRR. See many articles written by Bill Whitlock and Jim Brown, as well as app notes from That Corp. for background. You don't have to go with the full InGenius designs from That, but at least using an instrumentation amp configuration would give much better CMRR if that is a concern.
Filtering on the input for EMI/RFI/ESD is also recommended
about this, I'm currently studying this appnote from THAT:
http://www.thatcorp.com/datashts/dn133.pdf

capacitor on pin 5 of the OPA134 is obviously a mistake, thank you for pointing that to me.

about what I should do with the DAC output, I'm sorry but I didn't understand how I should fix that :-(
 

abbey road d enfer

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but at least using an instrumentation amp configuration would give much better CMRR if that is a concern.
An instrumentation amp has improved CMRR only when it has significant input gain. Basically CMRR increases as much as the gain in the first stages, which are cross-coupled.
Considering typical audio line levels and ADC range, there is rather a need for attenuation than for gain.
In this position there is no substitute for thoroughly paired (trimmed) resistors.
 

abbey road d enfer

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1) analog input and output levels. I followed the datasheet/eval.boards suggestions for both ADC and DAC, but those may not be the optimal levels for such application. Also I went for single-ended output on the DAC, but differential input for the ADC.
I couldn't help noticing the rather low value of the input resistors, which results in about 1.1kohm input impedance.
Although I admit it helps minimizing the input stage noise, it may challenge some sources. Most of the current audio gear has more or less standardized the input impedance for line level at 10-20k.
If I read correctly the specs, the input Fs range is 2.3Vp2p. Assuming you want to interface with typical line levels, you need to attenuate the input signal by a factor 10, which you can achieve by increasing the input resistors to 2.7k, for a resulting input Z of 5.4k, which is more in line with habits.
 

ccaudle

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An instrumentation amp has improved CMRR only when it has significant input gain.

That is over-simplified. Impedance imbalance in the output of the source device and impedance imbalance due to parasitic capacitance imbalance can degrade CMRR even with perfectly balanced resistors on the input side. The only help for that is high common mode input impedance, which you cannot achieve with the 4-resistor diff amp configuration. With an instrumentation amp configuration using FET input op-amps for the input buffers you can have higher value bias resistors, and with unity gain configuration buffers as is common for line level inputs you can bootstrap the bias resistors for even higher effective impedance at audio frequencies.
 

ccaudle

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about this, I'm currently studying this appnote from THAT:
http://www.thatcorp.com/datashts/dn133.pdf

I think DN133 is effectively out of date these days. These are not all directly applicable to what you are doing, since a lot are discussing concerns specific to microphone amplifiers, but they all have a lot of good general info:

DN140: front ends for That mic amps
AES preprint 6455, analog circuits for pro-audio
AES preprint 6261, benefits of InGenius input receiver IC
Interfacing mic preamps to AD converters
Analog Secrets Your Mother Never Told You
More Analog Secrets Your Mother Never Told You

about what I should do with the DAC output, I'm sorry but I didn't understand how I should fix that :-(

The reprint of the June 1995 AES Journal is a good place to start:
JAES June 1995 PDF purchase

The short version is that the benefits of a balanced connection come from the impedance balance of the hot and cold legs, which causes induced noise to be equal so that the differential receiver can reject the noise. Having symmetrical output swing has some advantages for crosstalk and headroom, but is not needed for noise rejection, so you can get almost all of the benefits of a balanced connection by making sure the impedance to local source ground is the same for the hot and cold leg.
Since you have a 100 Ohm build-out resistor on the op-amp driving the hot pin, if you put a 100 Ohm resistor from the cold pin to ground (preferably connected close to the output amplifier), you should have matched impedance to within a few percent at low frequencies where the op-amp feedback drives the closed loop output impedance to nearly 0 Ohms.

So when you connect that output to a balanced input you get the noise rejection of the balanced connection, but if you need to connect to an unbalanced input there are no worries about what to do with the cold leg, if it just gets connected to shield by plugging in a TS plug to your TRS connector everything still works fine, you just don't have the noise rejection advantages of a balanced connection. Best of both worlds.
 

abbey road d enfer

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That is over-simplified. Impedance imbalance in the output of the source device and impedance imbalance due to parasitic capacitance imbalance can degrade CMRR even with perfectly balanced resistors on the input side. The only help for that is high common mode input impedance, which you cannot achieve with the 4-resistor diff amp configuration. With an instrumentation amp configuration using FET input op-amps for the input buffers you can have higher value bias resistors, and with unity gain configuration buffers as is common for line level inputs you can bootstrap the bias resistors for even higher effective impedance at audio frequencies.
It seems you simply didn't catch my point.
I claim that a 3 opamp instrumentation amplifier with no gain in the input (no cross-coupling) has almost no CMRR improvement over the one opamp type. It is almost equally sensitive to resistor matching errors, which is usually dominant over source impedance unbalance and stray capacitance.
 

Dimitree

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I really appreciate the conversation guys, but since I’m not an EE unfortunately I only understand the 10% of what you’re saying 😃
One thing I realized is that I should not get the eval.board circuit and use that in a system like mine, those circuit are designed to show the IC capabilities and obviously not ideal for every application.
I’m wondering if I can just get any common input/output stages and use that togheter with those converters, or each converter has its own needs?
I’m not able to design my own analog circuit so of course I have to make some compromise
 

ccaudle

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thanks for the tip! I don't fully understand the [stubs] issue here, you mean that it would be difficult to design a PCB for that section?

I take it you do not have previous experience with RF or high speed digital PCB layout? The general issue is a conservation of energy problem where you want the energy sent into the PCB line by the driver to either all travel to the load and be dissipated at the load, or travel to the load, reflect back once, and be dissipated at the driver. This forum is probably a bit limited to go into the details of the physics behind that concern, but when you have a high edge-rate driver and multiple loads, there is no good way to address that concern without looking very carefully at the current paths and making sure that any reflections don't occur at a time and amplitude that could cause the clock receiver to detect two transitions when there should be only one. Daisy-chain style layout is one approach that can work with care, multi-output clock buffers are another.
If you want to learn more of the background then "High Speed Digital Design: A Handbook of Black Magic" by Graham and Johnson is one of the best classic texts on that. The logic families discussed are a little dated (at least in the version I have, I'm not sure if there may be some updated revisions), but it covers enough of the physics behind high speed digital design without getting too wrapped up in the math that it is relatively straight forward to apply to newer devices once you understand the principles.
 

Dimitree

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thank you for the infos. I'm currently reading the book you mentioned and learning about multiple clock distribution, terminations, buffers, etc.

Also I'm trying to understand how to get a better front-end for the ADC.
On the output, I added a 100Ohm resistor on each ring connection to ground.

Other than this, can you spot any other critical issue, specially on the clock scheme? I was a bit worried about clock phase and wondering if I should invert some clock signal before hitting the two ADAT chips
 

ccaudle

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Other than this, can you spot any other critical issue, specially on the clock scheme? I was a bit worried about clock phase and wondering if I should invert some clock signal before hitting the two ADAT chips

You will just have to look at the datasheets for the converters and the ADAT chips side by side and carefully compare the timing diagrams to see if there is any inversion needed.
Check the latency through the divider you have shown in the schematic and see what that does to the alignment of the various clock signals. If it delays those clocks too much you may have to reclock with a flip-flop and the higher frequency clock to get all the edges lined up again.

What quality level are you trying to achieve? The clock recovered from an audio signal (applies to S/PDIF, AES, ADAT, MADI, etc.) will be pretty high jitter. For low to medium quality interfaces you could use the recovered clock directly, but high quality would require a clean-up PLL, probably crystal based, but with careful design could probably use an LC based VCO.

Can you even still get those ADAT parts? I found a forum post from 2010 that said the Waveform Semi website was shutdown, and that there was no longer any R&D or even support, they were just selling parts until the sales volume dropped low enough to make that unprofitable, then they were going to shut down completely. The CoolAudio website mentioned in a previous post as a source of compatible replacement parts indicates that the original Waveform Semi (nee Alesis Semi) parts were discontinued in 2013. Were the CoolAudio the variants you were planning to use?
 
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