Digital Logic - done discretely

Rochey

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Folks,

Just wanted to share a good link with you.

http://www.hanssummers.com/electronics/misc/gates/index.htm

I was looking for a discrete implementation to make a not gate for one input, then OR it with the output of another.
rather than have to use IC's (from mouser etc) I can just use parts that I already have in my collection.
I managed to shrink the circuit from 2x IC's ($0.60) to 6 commonly used discrete components. (0.06)

Downsides/Compromises... voltage drop in diodes means that Low's will actually be 0.7V, and highs will only be 2.6V. That may be enough for some CMOS logic.
However, a voltage buffer should do the trick for that, if needed.

Please. Discuss ;)

I'm already aware that pcb and stuffing costs may be higher. For complex circuits, I'll always reach for IC's, but for quick'n'dirty logic jobs, this may be ideal.

cheers

/R

 

Rochey

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the pullup to +5V will always make the output 5V, unless something pull it down.

Assume A AND B are 5V, no current will flow through the diodes. (the diodes look like a high impedance).
If either A OR B are 0V, then current will flow through the resistor and diode, making the output point 0.7V (based on standard V-drop through a diode).

Not an absolute 0V, but not bad.

.
 

jdbakker

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Much more insanity here: http://www.transistorclock.com/

Discrete logic can be a good way to implement glue functions, but there are some pitfalls. The three things to keep in mind are voltage swing, slew rate and temperature effects.

Voltage swing: Especially CMOS inputs can be very picky about input levels that are too high/too low. Schmitt inputs and/or HCT logic helps.

Slew rate: Faster logic (including some microcontrollers) has minimum slew rates at inputs. Again, schmitt triggers can help.

Temperature effects: Something that works fine on the bench can easily fail at temperature extremes.

JDB.
 

burdij

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For your specific example of an inverter driving an OR, using the values shown in the diagrams in the linked article will probably not perform reliably. If you have a 10K resistor as the collector load of the inverter stage pulling up a line with a series diode and a 10K to ground, when the inverter output is high, the voltage at the 10K resistor in the following OR gate will be about 2.2V. This is below the transition voltage for HC which is 1/2 Vcc and slightly above the transition voltage of HCT which is 1.3V. Obviously, this problem limits the number of passive gates you can connect in series without regenerating the logic voltages.

You could still make this circuit work by decreasing the value of the collector load resistor of the inverter to increase the logic voltage level to the following stage. This takes advantage of the current sinking ability of the transistor. In the following stage, you could make the resistor to ground a lot larger, taking advantage of the higher input impedance of the following CMOS input. This approach, and the concept of passive gates in general, will not work if you are trying to feed the inputs of TTL-type devices as these depend on current sink through the inputs to work properly.
 

JohnRoberts

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For the vast majority of my mostly analog career, that (discrete) was the only kind of logic I did.  I do recall one job interview back in the late 60's where I was asked to make a bistable FF out of two transistors. (I got hired, but was drafted into the army before I could take the job). :'(

I did some psuedo digital designs with 4000 series CMOS logic, and one part I used for some outside the box tricks was the CD4007. It had several uncommitted P and N FETs that you could mix and match to make obscure logic functions.  I even used one to make a voltage to period clock source.

JR
 

Twenty Log

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They have AND gates and OR gates and the like, but not MAYBE gates....  Indeed this gets back into Analog (where digital is a subset)... definitely run this through a XSpice style of simulator to get the mixed signal realms or a lot of hand calculations...

Cool...
-chris
 

PRR

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> I was asked to make a bistable FF out of two transistors.

Sounds like free points. I'm always shocked to find techs who don't know what a flipflop is, and can't imagine it done in loose transistors.

Lancaster(?) calls the unbuffered diode gate "Mickey Mouse Logic" and gives good tips when it may be good and when you may regret it.

You do realize that ALL logic problems can be solved with only NAND gates? Stock a quad 2-in NAND chip and DeMorgan an answer. Just NOR works too, and in this case it saves a gate. NAND was customarily cheaper to implement; not that you'd know the difference today.

> a not gate for one input, then OR it with the output of another.

Well, at least there is no need to teach DeMorgan's Theorem. It is very applicable, but in this case it won't save a part. Only experience and dirty tricks can reduce this problem.

The 3-part solution works, I think, if A will pull-up to the rail (unloaded classic CMOS).

It assumes inputs never float.

It assumes that speed and cleanliness are not critical. A mute or pad relay. Not a pulse counter.
 

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Rochey

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PRR, every time I see your name in the replies to one of my posts, i wonder if i'm in for a few sharp words, but always know it'll be a valuable read.

thank you sir. i'm off to digest your post one more time  :)
 
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