Dimitri Danyuk's approach to P48 mic output

[homero.leal]

Some time ago I found this schematic from Dimitri Danyuk, proposing a new approach to a P48V mic output:


AFAIK this is the only schematic have seen which doesn't require the recommended matching of PNPs HFE value (LIke the Alice/Schoeps design), matching coupling output capacitor values (like some of the Zapnspark designs), or a transformer to provide the mic output.

My understanding is that it uses an Integrator (R2, R3, C3, IC1 and D1) to balance DC voltage levels at XLR2 and XLR3 lines, and the signal it's not fully balanced, I mean... the signal output is only at XLR2 while XLR3 remains at a fixed DC point.

While the DC voltage is balanced at XLR2 and XLR3, my main concern is... What about line impedance?

Anybody knows how to figure out output impedance for XLR2 and XLR3 lines? I have read that this is a very important factor to CMRR, and that's the reason of my question.

You could have a look at Dimitri's original article at:

https://www.edn.com/condenser-microphone-uses-dc-coupled-impedance-converter/

Thank you and kind regards!

HL

 

[Bo Deadly]

Impedance of pin 2 is R6 and then behind that Q3 emitter which is driven to low impedance but depends on impedance at base which is high at AC. Impedance of pin 3 is R7 and then behind that Q4 emitter which is driven to low impedance but depends on impedance at base which is low at AC.

Because Q3 and Q4 emitters are driven low impedance, I would say R6 and R7 are going to be dominant enough that using 0.1% resistors might actually make a difference in CMRR connected directly to a test rig. But the presence of 75R on each line is going to limit CMRR in practice because you want really low source impedance for great CMRR to minimize the influence of differences in the line and input. At least Schoeps doesn't have those resistors.

Stated another way, the 75R might be there specifically to make up for the difference in emitter impedance Q3 Q4.

Also the circuit is a little too clever. The JFET is self biased. It might be important to protect that gate with a guard trace. The op amp cannot be just any op amp either. The inputs are held at V+ so they have to be JFET input without any fancy protection circuitry on the inputs.

But it might have some endearing qualities that I'm just not seeing right now. Definitely would have to simulate to completion in LTSpice before doing anything else.

That's my first glance cursory impression anyway.

 

[abbey road d enfer]

I can just reiterate what I wrote in the Micbuilders group:

AFAIK this is the only schematic have seen which doesn't require the recommended matching of PNPs HFE value (LIke the Alice/Schoeps design), matching coupling output capacitor values (like some of the Zapnspark designs), or a transformer to provide the mic output.

It has no coupling cap after the FET, so both legs benefit from a very low drive source (note the Darlington between the FET's source and the output transistor).
The impedance is just about a few ohms more than the 75 ohm resistors. The impedance of the hot leg is constant with frequency, while the impedance of the cold one increases slightly at LF (90r @50Hz for the cold leg, about constant 80r for the Hot) due to the capacitive source impedance.

However, claiming that it does not require pairing the transistors is somewhat misleading, because it implies that unmatched transistors are the cause of BAD performance. Actually, that is a very common misconception.
I see people getting anal retentive about matching Hfe to a fraction of %, which actually does not result in better CMRR.
Here is why:
In a standard Schoeps/Alice circuit, the Hot and Cold legs are driven by different impedances. The only workable way to properly balance impedances is to make the output resistor on the leg driven by the FET's source slightly lower than the other and making the coupling capacitors large enough (470+nF).

In other words: unmatched Hfe of output transistors is not the primary cause for bad CMRR.

With the proposed circuit, it is true that the difference of output Z due to Hfe mismatch is probaly less that 3 ohms (even less if the transistors are in the same gain range), except at LF.
Remember that CMRR degradation is due to absolute difference between legs, not ratio. Adding equal resistors does not improve CMRR; they are here for stability with capacitive loads and EMI/RFI protection.

While the DC voltage is balanced at XLR2 and XLR3, my main concern is... What about line impedance?

The output impedance is dominated by the 75R resistors.

Anybody knows how to figure out output impedance for XLR2 and XLR3 lines? I have read that this is a very important factor to CMRR, and that's the reason of my question.

The simplest way to analyze this circuit is simulating it with Spice.