> why do I need to add a resistor to divide V down at the base?
You need to learn to do basic DC analysis. Not precision analysis: at-a-glance could-this-work? analysis. Not rely on dubious factoids like "hold the base at 1/2 supply". (Maybe you are thinking of Emitter Follower?)
You seem to understand that you might pick a base resistor for very low voltage drop due to base current. Good.
So you have base near Zero. Where is the emitter? For any happy transistor, about 0.6V lower. So emitter is at -0.6V.
Now you have an emitter resistor and a collector resistor. For equal-but-opposite outputs, these two will tend to be equal values. Just to put some numbers on the thing: emitter is at -0.6V, rail is -15V, R2 has (15V-0.6V)= 14.4V across it. Say you run Q1 at 1mA emitter current. To make that happen, R2 must pass 1mA at 14.4V. R2 must be 14.4K. R1 must be equal to R2, also 14.4K. Collector current is almost equal to emitter current (for any good small transistor, 0.3% to 2% low). The drop in R1 must be 14.4V also. (Or 14.3V if you sweat the small detail.) R1 starts at +15V, so 14.4V drop forces the collector to +0.6V (or 0.7V).
Q1 sits there with +0.6V collector, -0.6V emitter. It has 1.2V of drop collector to emitter. Any modern transistor will carry 1mA even with just 1.2V across it.
The DC analysis appears "OK". (But note that with +/-5% parts, with R1 5% high and R2 5% low, R1 could try to drop 15.8V, which implies that the collector winds up at (15V-15.8V)= -0.8V, which makes collector-emitter voltage negative, and the transistor won't work right.)
Now swing the base up and down with 0.1Vpk signal. Emitter swings up and down -0.5V to -0.7V. Collector swings down and up +0.5V to 0.7V. Worst-case, the transistor still has 1.0V across it, still conducts and does the right thing. OK.
0.1Vpk is a small signal. What do you really need? Your output should be capable of 7Vrms, 10Vpk. This is across two outputs, so each one only needs 5V peak. Your output buffers are unity gain. Your splitter must be fed 5Vpk at the base and make 5V swings at both collector and emitter.
OK, momentarily bring the base up from zero to +5V. Emitter wants to follow to +4.4V. Collector was sitting at +0.6V and must swing down to -4.4V. This says the collector is more negative than the emitter. (On an NPN) this won't work as a Transistor.
What will actually happen may not be intuitive. If your signal source is strong, the base will go to +5V, the emitter will go to +4.4V. Because the collector-base voltage fell to zero, there is no transistor action, no base current gain, but the base-emitter junction will act as a diode and the source will pull R2 up to near 4.4V. And the base-collector junction, normally reverse-biased, becomes forward-biased and acts as a diode. The source will also pull R1 up (instead of down like a good phase-splitter should). So you have heavy loading on the source (it is pulling both R1 and R2 without any boost in Q1) and two IN-phase outputs.
What this does to your load is a good question. A good diff-input will ignore the in-phase signals and give zero output. So the receiver will get the right signal up to about 0.5V-0.6V positive peak, then wobble a bit (the two junctions of Q1 won't go-diode at the same voltage), then fall to zero.
OTOH, negative inputs are handled perfectly, down to nearly -15V input.
Note that I've used no fixed assumptions, only general current relations in a happy transistor, the facts that modern small BJTs have Vbe roughly 0.6V and Hfe above 50. You can change the assumed current to 0.01mA or 100mA and get the same results. You could make R1 much smaller than R2 and handle larger input, but now the collector output is smaller than the input or the emitter output, which makes a crummy phase splitter. I cheated with a calculator, but all this math can be done on fingers, 1-digit accuracy, and the "impossible result" is still clear.
Using the same type of thinking, you can easily find the approximate best-point for the Base. Once you find it, it is "obvious". It is in fact as simple as "1/2 supply", but the fraction is different.
If you keep following such analysis, you can make this plan "work". You should be able to see that the overall gain is "2" or a little less; line drivers usually accept signals at lower internal levels and boost them up, so a gain of 2 may not be enough on its own. The maximum output of each side is much less than your total 30V supply voltage; this may be ample for modern studio levels but does not leave a heap of headroom and is mildly inefficient (even before we get to Class A non-push-pull). The output is also constrained by the relation between the load (which could be 600 ohms) and R6 R8 trying to pull the load in the direction that Q4 Q3 can't pull.
> the 2nd order characteristics of the first stage.
I grant that, if the buffers are so wastefully beefy as to have no distortion, then Q1 will give an even-order characteristic to the overall transfer. However the THD of a cathodyne is vanishingly small right up to the point that it gives up. It has GOBS of negative feedback, especially with a BJT and higher rail voltages (or CSS loading). As a ruff rule-o'thumb, say 25%*0.020V/Vrail, or in this case around 25%*0.020V/15V, or 0.03% 2nd Harmonic (and much lower 4th, 6th, etc) at half max voltage. Far under 0.01% 2nd at nominal line level. That's with R1 R2... if these are CSSed and the buffers are very high impedance, the THD will vanish. If you want "color", this isn't the way.
I don't want to discourage you. That's why I walked-through an analysis that Wavebourn and I do "at a glance" (after long practice). Until you can see, without a lot of hints, why Q1 base probably won't be near-zero, you are just drawing pretty pictures.
And isn't that a SPICE program? In a way, I'm glad you apparently didn't run SPICE on it. SPICE can be handy for finding 8-place answers. But it is a blundering idiot who won't tell you that your circuit does not work as you hoped, much less "why?" IMHO, it is essential to be able to do the martini-napkin sketch and find happy rough-answers in your brain, which can be confirmed by "low-pay idiot assistants" like Grad Students, Junior EEs, (no offense!) or SPICE (offense intended).
