Feedback on my first pcb layout

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JMan

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Hi Everyone,

After a great deal of struggle over the last few months trying to figure out just how to use pcb layout software, I finally sort of think I've got Eagle working for me. (I've tried others, but my brain doesn't seem to like the way these programs function).

Anyway, I've manually laid out a board for the Helios 22113 amp with the intention of using it as a makeup amplifier in an RS127 as @mike has done in his project here. Because there will be limited space, I attempted to make this board as compact as I could.

Since I know nothing formal about pcb design and layout, I'd really like feedback on this. I did double check everything against the schematic after I finished and ran the ratsnest check thing in the software, so I know that the connections are all correct and the circuit should theoretically work. But in terms of layout, I feel like I see people discussing routing practices and physical layout and such things that are completely foreign to me and would like additional eyes on it. I managed to get all of the signal routing on one side of the board and ground connections reasonably well consolidated on the other side. (Maybe this is good? I have no clue. It seemed like a good idea.) How did I do?
 

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I remember very well my first PCB layout. Believe me it does get easier with practice.

I would recommend you move Q6 down to the bottom right of the board so it is nearer its associated transistors. If you are going to use a bus bar ground system then power should enter near the output stage not near the input stage so you could move the power in connector down to the bottom left. As the power bus seems to be the only net you have on that side of the board you might as well flood the whole layer with it.

Cheers

Ian
 
Could you post a copy of the schematic as well (Showing the reference designators that correspond to your layout)? It makes reviewing the board layout easier, even for very simple designs like this.

A couple things that initially pop out to me in the layout:
- There is no local bypassing capacitor(s) from 24V to GND. Without being more familiar with the circuit, I would add least add provisions for a larger bulk capacitor (10 µF or so, ceramic or electrolytic) in addition to a smaller value, low ESR capacitor (ceramic)
- It couldn't hurt to increase the 24V trace widths, as well as your output signal traces (especially if you expect this thing to be driving any substantial amount of load)
- Usually for this type of simple 2-layer layout, I would just flood the entire bottom side with ground. This creates a nice low impedance return path and avoids having to un-necessarily extend signal traces to the left side of the board that are just routing through a component to ground. Instead, ground can just be accessed anywhere.
 
Thanks @ruffrecords and @dom !

You know, I probably spent 45 minutes just trying to flood the bottom layer instead of using that darn bus bar for ground, because I was pretty sure that would be the first suggestion I would receive. The biggest problem was that while I was able to flood the layer, it would invariably isolate all of the pads, including the ones that I needed connected to ground, and I couldn't get it to connect where I wanted it to. This CAD software stuff really isn't intuitive for me. I'll have to spend more time googling and playing around with it, but if anyone knows an easy method in Eagle... 😅

Ian, I'll definitely make those improvements. Okay, so I'm taking notes -- transistors that are associated (I take this to mean interacting or working in the same part of the circuit, e.g. Q6 and Q7) like to have some physical proximity; and power entry should be nearer the output if using a ground bus (less important if simply flooding the ground layer, or still good practice?).

Dom, thanks for you feedback. The schematic that I used is in the post that I linked to earlier. I can for sure make the 24v and output traces wider (frankly, I could probably just do that to all of the top layer traces). Is there a particular width you'd say is sufficient? I ask because my brain doesn't intuitively connect the trace measurements in the software to any practical considerations yet. Those traces are currently 0.6096 (mm? I don't even see units).
 
Here are some rules I follow when designing a PCB:
- input and output should be on opposite PCB sides
- the placement of the elements should be logical and spread from left to right as well as schematic
- the output transistors should be close to each other (they share usually the same heatsink and thermal stabilization parts)
- etc..
last one:
- if you have a lot of space on the board to write in large font the name, surname, logo, etc. PCB is poorly designed, you have too much unused space :)
 
Sorry I can't help with your ground fill issue (I'm not familiar with Eagle usage). It's probably worth figuring out how to do. I don't think it's essential for this particular design since it looks like most of your trace runs are already nice and short, and your ground bus plan is fairly wide, so I think it'd more than likely be fine as-is. But, filling plane shapes are a pretty core part of most layout designs, so better to figure out how to do it now rather than later if you intend on doing more PCBs in the future.
 
You know, I probably spent 45 minutes just trying to flood the bottom layer instead of using that darn bus bar for ground, because I was pretty sure that would be the first suggestion I would receive. The biggest problem was that while I was able to flood the layer, it would invariably isolate all of the pads, including the ones that I needed connected to ground, and I couldn't get it to connect where I wanted it to. This CAD software stuff really isn't intuitive for me. I'll have to spend more time googling and playing around with it, but if anyone knows an easy method in Eagle... 😅
That sounds to me like you didn't name the polygon correctly. If the polygon has the same name as the ground fill you currently have, it should automatically connect.
 
input and output should be on opposite PCB sides
I'm going to disagree with this suggestion. A lot of chassis have all input and output on the back of the chassis, so having input and output on opposite sides of the PCB doesn't necessarily make sense if they end up on connectors physically close together on the chassis.
Also, if input and output are on opposite sides of the PCB you have to think extra about shield current flow, and how you are going to connect shields on unbalanced connections without getting shield current flowing across your PCB (aka "pin 1 problem"). It is a little easier if every in and out is balanced, but then you still have to think about chassis impedance and where the currents are going to flow, e.g. do you have any separate pieces of sheet metal that comprise the chassis which could have less than good contact. That all just gets easier to deal with if all of the I/O is kept close together on the same edge of the PCB.

I probably spent 45 minutes just trying to flood the bottom layer

There are two different terms/concepts in most PCB software, "plane" and "flood" or "pour." A flood or pour area is a defined shape that has all the copper left in place, but you have to explicitly give that area a net name if you want it to connect in to an existing circuit node. Since you define the shape it can be a large or small as you want.
A plane means all (with some exceptions) the copper on the entire layer is left in place, and you have to tell the software what circuit node connects to that plane. Usually it will be either your GND node, or one of the power supplies. The exceptions are where a connection to a different net breaks through the plane. Usually you won't have many on a two layer board, but on a multi-layer board where a connection goes through the plane to connect to a different layer, there will be a small circle of copper left which is necessary for good adhesion of the copper plating in the via during manufacturing. Depending on your settings, there can be a small pattern etched into the copper around vias to the plane to provide a little bit of thermal resistance to make it easier to solder a wire or component lead which has to connect. It looks like a little "+" sign with the hole in the middle, and the outside edges of the arms connecting into the plane. Without that it becomes really hard to solder because the copper plane transfers the heat away from the via and component lead so efficiently. That setting would usually have something like "thermal relief" in the name, and usually some indication that you are setting automatic thermal relief creation on or off.
 
You all are so great! I'm learning a lot from this thread.

I did finally manage to get the pour to work. It was indeed a naming problem. So simple once it was pointed out, but I would have never thought of it on my own. @ccaudle I am going to read your post a few more times when I've had more sleep, because I can see that there is a difference between the "pour" and "plane," and I would like to understand it better.

I've done some work on rearranging the board, and I have increased the width of the traces. I still want to do some more fiddling this week.

You all...this CAD stuff...I'm so impressed with all of you who understand it. I work in Adobe Illustrator all the time and am very proficient in it, and Eagle looks enough like graphic design software that I just expect it to work in the same way, but it does NOT (I mean, there's obviously a certain amount of overlap in concepts, but the practicalities are shockingly different).
 
You all...this CAD stuff...I'm so impressed with all of you who understand it. I work in Adobe Illustrator all the time and am very proficient in it, and Eagle looks enough like graphic design software that I just expect it to work in the same way, but it does NOT (I mean, there's obviously a certain amount of overlap in concepts, but the practicalities are shockingly different).
It gets worse. If you take the next step and venture into mechanical CAD you will find the user interface is again quite different to any other CAD program you have used. It is pretty much a modern rite of passage.

Cheers

Ian
 
It really pays to make a sketch (even on paper is fine), that is to scale, and shows where you intend to locate anything that connects to the board. The first two things you need to start with are a) a rough estimate of the size of the board, and b) the locations of any/all connections to the board. Pads/connectors/pins/cables/etc should be the very first thing that is placed, and then go from there.
 
I'm going to disagree with this suggestion. ...

Fine with me. I have to admit that I am influenced by older PCB design schools in times of transition from p2p technology, and more intensive work on PCB designs for audio and RF amplifiers using OrCAD on DOS OS. I always follow this rule, even when the input and output connectors are located on the same back side of the device. And I've never had a problem with grounding. I still think that PCB design is an art form, and that if you want to do it right, you need to know completely how the circuit works, where the local current loops are, and where unwanted feedback can occur. In such a design you can’t go somewhere from the input and end up back again in the same place at the end of the road.:)
 
Out of curiosity, when you say "opposite sides" of the pcb, what exactly does this mean? I can think of at least three variations of this idea, and I probably don't have the parlance down well enough to understand if one of them is implicit here.

1. One on top layer, one on bottom
2. Both situated on the same edge of the pcb (much like my original layout was), but at opposite ends from one another
3. One situated on one edge of the pcb (let's say left) and one situated on the opposing edge (in this case, right)

Of course, I guess that it could be some combination of these as well...
 
Out of curiosity, when you say "opposite sides" of the pcb, what exactly does this mean?
Third example. As in discrete opams.

A bad example (one of) in your design is the track that connects the emitter of output transistor Q6 and its resistor. The highest currents flow through this track and it has the highest AC voltage. It passes close to the R7-R10 right pin connection and there is a high probability of positive feedback at higher frequencies. Same situation as if you added a small capacitor of a few pF between the + input and the output of the opamp. Poor PCB design actually adds parasitic elements to your schematic.
 
A bad example (one of) in your design is the track that connects the emitter of output transistor Q6 and its resistor. The highest currents flow through this track and it has the highest AC voltage. It passes close to the R7-R10 right pin connection and there is a high probability of positive feedback at higher frequencies. Same situation as if you added a small capacitor of a few pF between the + input and the output of the opamp. Poor PCB design actually adds parasitic elements to your schematic.

How high a current though ? From looking at the layout and experience (to quote a popular comedian - "I've done no research") I'd guess that it wouldn't be a problem - the track isn't that close. Although an extended 0V Copper Pour on the bottom layer and/or 0V fill on the top layer would help.
 
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Third example. As in discrete opams.
Okay, thanks for the clarification.

A bad example (one of) in your design is the track that connects the emitter of output transistor Q6 and its resistor. The highest currents flow through this track and it has the highest AC voltage. It passes close to the R7-R10 right pin connection and there is a high probability of positive feedback at higher frequencies. Same situation as if you added a small capacitor of a few pF between the + input and the output of the opamp. Poor PCB design actually adds parasitic elements to your schematic.
I mean, yeah, I get it. As an hobbyist, my first attempt ever at designing a pcb wasn't a home run and I probably shouldn't be expecting any calls from the space program. To set expectations appropriately here, maybe it's worth mentioning that I have zero background in engineering and have been trying to teach myself about electronics for about two years in my spare time, but a lot (read: most) of the subject is still way over my head. So there is a lot of learning by doing, and there are many things (like your example with the Q6 emitter and R7/R10) that I don't even know to look out for. "Poor PCB design" is (A) an abstract notion to me because I lack the experience to even understand what that means in practical terms -- hence this thread -- and (B) probably just where I'm going to live for awhile as I try to get my head round it.

Thanks for your help along the way! (And also, apologies that my very next post is going to be my revised board where I have failed to correct literally anything that you mentioned. I'd done the work before you responded here.)
 
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Okay, here's what I've done revision-wise so far.

-I did manage to flood the bottom layer for the ground connections (EDIT: I initially posted a picture of the board without the flooded layer, but that was confusing so I've re-uploaded with the pour visible).
-I widened all of my signal traces.
-I also moved the output transistors closer together and generally tried to consolidate and organize the board a bit more (someone up above noted that my big blank area was a design flaw).

I'm sure it's still far from perfect, though, so what can I still do to improve it? (Second picture added because it's a little less busy and might be easier on the eyes).

Screen Shot 2022-01-24 at 3.43.33 PM.png
Screen Shot 2022-01-24 at 3.44.19 PM.png
 
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Why aren't you using the bottom of the board?
Yeah, great question! As I mentioned, I will be flooding the bottom layer and all of my 0v connections are made there. I guess in my mind, when I first started messing with this, if I was flooding that layer then I shouldn't have other signal traces on it. That was sort of a tacet assumption that I hadn't even thought to challenge as I went along. Is that incorrect?

EDIT: Just changed the image in the post above to one that shows the bottom layer.

The schematic that I'm working from is linked in my first post. I'll link it again here. I didn't want to put it in this thread directly because it is someone else's work here on the forum, so I linked to their post instead.
 
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