Forced Class A opamp

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chrissugar

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Just a question.
Is there a consensus about which method is better to make an opamp (for example 5532) to work in class A, to connect the output with a 10K resistor to the positive or negative supply. I know that Ficusrote connect the out to the positive, but I also read about the fact that it would be a better idea to connect to the negative because that would make the NPN trany to do the job.
Please don't say "Try both and listen" because I don't have time to reinvent the wheel. I'm just curious if there is any consensus about the influence on sound.
Anyone done some listening tests and measurements?

chrissugar
 

bcarso

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I remember some measurements Rich May did years ago with the LM833 and he loaded the output to the negative rail. He had already thought that it improved the audio quality and wanted to see some measurements to back up what he heard.
 

featherpillow

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I've never experimented with tying the output of an opamp to the positive rail, just the negative, so I can't give you any comparison there.

I can tell you that you're better off using some type of current source other than a resistor in an application like this.

For example, a FET operated in the saturated region presents a high impedance and low output conductance it to the opamp. It has the potential to offer two things that the resistor can't--ample current and a very light load.

A recommended reading on the subject is the Vishay Siliconix AN103 application note, found here

Another good read is a thread from a few weeks ago about this subject--bcarso had proposed a neat bias method using a BJT and an LED.
That's here.
 

adrianh

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Chris;

Not exactly your answer in the Linear Tech datasheet for the
LT1115 they have a JFET set for 2ma connected to the negative rail.

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1026,P1293,D1612
 

featherpillow

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you probably want more like 5ma
I've always thought so, too, but for different reasons. The amount of current needed for biassing does depend upon the load you drive. And yes, if you're using a FET, capacitance is an issue--read some of the comments from PRR and bcarso in Tom Waterman's thread.

But, if you're buffering the class A stage, you won't need to worry about the opamp driving a cable, you'll let the buffer do it. I wouldn't want to drive a cable with this something like this anyway...

I have to assume though, that Misters Jung and Markell knew what they were doing when they designed that stage with a 2ma bias requirement.

Linear Tech datasheet for the LT1115 they have a JFET set for 2ma connected to the negative rail.
Actually, I think that's what brought this up--skim through that Jung/Markell thread over in The Lab if you haven't already.

Since no one has answered the question here--neg bias vs positive bias--I'll offer a comment: from what I've read about bias, we choose a negative rail to handle the work here because NPN's typically behave better than the PNP's. I've read before that they are faster than the PNP's are. I have no idea if that's true.
He had already thought that it improved the audio quality and wanted to see some measurements to back up what he heard
bcarso, are you holding out on us? :grin:
 

[email protected]

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[quote author="buttachunk"]just put a single ended (common emitter buffer) output after this stage.[/quote]

Hey Butta! Now that is a neat idea. Instead of something complicated like the LT1010 just use a simple emitter follower.
 

chrissugar

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Thank you all for your responses.
Interesting is that I didn't read the "Constant Current Sources" thread and there is some good info there.

I was just curious if anyone did some tests to see if there is any audible difference, and functional difference between the two versions.

My idea was to mod one of my SSL comps and change all the 5532 and 5534 opamps to class A and see how the sound will change.

chrissugar
 

strangeandbouncy

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Finally, a degree of explaination!

For years I have pondered on various expensive boxes that boast Class A operation, yet are full of chips such as 5534's. I always thought that it was not possible . . . could anyone please be kind to a simple soul and explain just how this is possible? I guess there must be some disadvantages too, or everyone would be doing it! Perhaps reduced headroom(?) Maybe some kind person could direct me to some appropriate info?

I am very intreagued . . .


ANdy P
 

bcarso

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Disadvantages: Reduced ability to output current of the other polarity; reduced loop gain if the loading is via a simple resistor; increased quiescent power dissipation; increased power supply current; higher parts count.
 

Gus

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FWIW I built a passive EQ phono preamp using a TL074(about 1980). I used 5.6K resistors to -15V. This was inspired by a Jung and White article and letters in TAA back about 1979/80 IIRC. I got the eq math from a AES paper by W. Jung.

The chip runs hot! 4 opamps in one package with resistor pulldowns might not been the best thing to do.

If you use higher voltage +- supply you might want to add thermal epoxied heatsinks to the chips. It is easier to find now because of overclocking PC stuff. Arctic Alumina from articsilver.com should work.

The heat might cause offsets to drift as well.
 

chrissugar

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There are 3 opamps worth to change to class A per channel.
http://www.gyraf.dk/gy_pd/ssl/ssl_sch.gif
The input 5534 are working into a light load so I think at this place it is not a problem. The 5534 from the VCA circuit are not in the signal pass so no reason to do any change.
I suppose in the SSL comp only the output drivers would be problematic if the forced class A is applied. Maybe if it used with a high Z load it will work OK.

chrissugar

P.S. By the way I discovered a very interesting distortion patern in one of my five SSL comps. They all are identical, with measured components to be identical in all five. They all have a very low distortion but one has an interesting patern. Four have all the harmonics, the second is the highest, then a bit lower is the third, then even lower the fourth and all the components dissapear in noise let's say in an exponential way. The "different" one has a distortion patern where the even order harmonics have the same value like the other four SSLs but the odd harmonics have extremely low values compared to the even ones. Looks very much like a tube distortion patern. I had no time to investigate what is the source for this but will do some tests to see where this thing is comming from. I suppose it is from the VCA but I will see after tests.
 

strangeandbouncy

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hi,
I have been trolling through all my op-amp literature, and I can't find any examples of class A anywhere! Can anyone explain what needs to happen, or be so kind as to point me towards some literature that can help?

ANdyP
 

bcarso

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That's an interesting discussion. I take issue with two points: his early statement that this arrangement "reduces thermal variation" needs to be qualified at best. The statement that you need to isolate the capacitance of the FET current source from the op amp output is pretty silly for the FETs he is using, which run about a pF at typical bias voltages.

"Reduces thermal variation"---compared to what, and what is the measure?

If we were able to raise the quiescent current in the output stage of the amp and operate it class A internally, then indeed the variation of chip dissipation when delivering current to a load could be smaller as a delta dissipation number, compared to a lean class AB output bias.

For the latter, driving a resistive load a given output device would have peak dissipation at about half of the given supply rail voltage out, and close to zero at max out and zero out. As a percentage of quiescent dissipation the ratio swing could be huge.

But that---the ratio---is not what counts for the thermal shift in other stages on the die---it's the delta dissipation and hence delta temp. I.e., if we're dissipating 100mW and we have a delta 10mW, it has virtually the same effect on a nearby input stage being heated and cooled as when we are dissipating 20mW and have the same delta 10mW. It seems counterintuitive, but aside from the shift in tempcos with absolute temperature and tiny shifts in heat capacity etc. is nonetheless true.

Now, with the situation at hand, with a current source load forcing class A, the current source is only distantly thermally coupled to the IC. So the dissipation swing with output voltage, as a delta P/delta T, may well be larger. Moreover, the chip designers may have done a layout in which roughly the same dissipation and temperature swings were assumed for both halves of the output stage, and we are now making this highly asymmetrical by shifting all the action to the NPN.

Of course minimizing dissipation shift is not the primary goal of forced class A biasing. But if this were a major concern---and it well may not be---what this suggests is tailoring the loading current sink's current to keep the chip dissipation constant with signal swing :grin:
 

PRR

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[quote author="bcarso"]reduced loop gain if the loading is via a simple resistor[/quote]

Unlikely. If the drop across the DC load resistor is over ~300mV, the EF gain is over 0.9. In this case we seem to be looking at 15V bias, so (neglecting AC loading) the gain is OTOO 15/(0.030+15) or 0.998.

The AC load must be equal or greater than the DC load if we hope for 0.5*Vc signal swing or better. Gain now drops to 0.996.

We also need a hi-Z load to the opamp, more than maybe 1K-10K. The AC+DC loads are multiplied by Beta, so they should not sum much lower than maybe 20Ω (my Tori is marginal this way).
 

bcarso

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But for a lot of op amps the EF presents a load to the previous stage of about beta times the output load---it's not the EF gain that I'm concerned about so much as the gain at its base.

Rich May used to like to load the node ahead of the followers with resistors so that the gain was to first order not affected by the output load. I was bothered by that since the overall numbers looked worse, but I think I am coming round to his point of view more and more. He did really listen, and when he had the freedom to do so came up with some good-sounding stuff.
 

PRR

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> the EF presents a load to the previous stage of about beta times the output load---

Sure.

If we are driving the same load as before, the op-amp is now working easier.

If the load is even semi-sane, a few hundred ohms, the op-amp is unlikely to be strained.

My Tori pushes the limit. Load down to 32Ω, possibly a 20Ω DC load, total load about 12Ω. With 500Ω-capable 5532 and Beta of 40, "OK". With TL072 and Beta=20, it could be sad. In fact because the TL072 has Zout over 300Ω, its gain is down to less than half. But 32Ω phones don't need much net voltage gain.
 

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