FPGA-based SID chip synthesizer questions

Consul

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This forum needs some activity.

I have a couple of SID chips, and I'm hunting around for a couple more. My goal is to make a SID-based polysynth using an FPGA. I have a Nexys2 board with a Xilinx FPGA (1.2-million gate-equivalent - what that means is hard to explain, but you can mostly think of it as exactly what it says) which uses 3.3V power and logic. The SID chips need 5V. Hence, question number one.

I do know that level shifters exist and are out there, but the best ones for my application are all very small (smaller than SOIC) surface mount packages that I'm not equipped to deal with. There's a way to do it with an FET per line, but I keep running into confusion about the spec of FET I need to make that work. I don't think I need bidirectional shifting, so I'm wondering if simple op amp circuits with appropriate voltage gain, as well as some current gain, would work.

That actually brings me to a design conundrum. For a polysynth, I could drive all four SIDs with the same set of address and data lines (5 address, 8 data) so that they all have the same settings at any one time. For a basic polysynth, this is fine, and thirteen amplifiers with enough current gain to drive all the loads wouldn't be so hard. But if I want to add a solo mode, that would mean that I'd want to be able to send separate settings to each chip, which would then all fire at once from a single note on. So that means four 8-bit data buses and a 5-bit address bus (they can all still share that one), for a total of 37 amplifiers. That seems like a lot of work.

My second question is to do with MIDI and optoisolators. The first thing I plan to get working is processing MIDI in. I understand the spec just fine (it's simpler than RS232, really), but I'm wondering how the optoisolator works. Does it have its own power rails, or can I just treat it like a passive component?

Thank you all for the help! After taking a digital design class using FPGAs and VHDL, I've finally gotten excited about electronics again.
 

JohnRoberts

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You can probably buy 5V logic chips that will respond to 3.3V input in reasonable sized packages, a lot easier than rolling your own from discrete. Especially if you want to pass data reliably at decent clock rates.

JR
 

Andy Peters

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dmlandrum said:
This forum needs some activity.

I have a couple of SID chips, and I'm hunting around for a couple more. My goal is to make a SID-based polysynth using an FPGA. I have a Nexys2 board with a Xilinx FPGA (1.2-million gate-equivalent - what that means is hard to explain, but you can mostly think of it as exactly what it says) which uses 3.3V power and logic. The SID chips need 5V. Hence, question number one.

I do know that level shifters exist and are out there, but the best ones for my application are all very small (smaller than SOIC) surface mount packages that I'm not equipped to deal with. There's a way to do it with an FET per line, but I keep running into confusion about the spec of FET I need to make that work. I don't think I need bidirectional shifting, so I'm wondering if simple op amp circuits with appropriate voltage gain, as well as some current gain, would work.

I was able to find a SID data sheet, which helps ... and the Nexys2 board has a Spartan3E FPGA.

Xilinx talks about S3E 5V compatibility here.

The short answer is:
a) Set the output-only (from the FPGA) pins to use an IOSTANDARD of LVCMOS33. The SID logic inputs need only 2V for a valid logic high, which is easily driven by LVCMOS33 outputs which swing to the 3.3V rail. No level translation needed.
b) For the bidirectional data bus, you're kind of stuck, because the series current limiting resistors required to keep the FPGA inputs from burning up make it difficult for the output to drive the SID inputs to the appropriate level. Do some math to check this. I wouldn't do it.

I assume you'll have to build some sort of board onto which the SID and its related parts need to be installed, and you're afraid of SMD. You shouldn't be, but anyways, the NXP 74LV245 comes in DIP and will work as a level translator given a 3.3V supply.

That actually brings me to a design conundrum. For a polysynth, I could drive all four SIDs with the same set of address and data lines (5 address, 8 data) so that they all have the same settings at any one time. For a basic polysynth, this is fine, and thirteen amplifiers with enough current gain to drive all the loads wouldn't be so hard. But if I want to add a solo mode, that would mean that I'd want to be able to send separate settings to each chip, which would then all fire at once from a single note on. So that means four 8-bit data buses and a 5-bit address bus (they can all still share that one), for a total of 37 amplifiers. That seems like a lot of work.

If you have the I/O available, then drive each SID from its own FPGA pins. The FPGA won't have any problem doing so. Of course you'll need four data buses.

My second question is to do with MIDI and optoisolators. The first thing I plan to get working is processing MIDI in. I understand the spec just fine (it's simpler than RS232, really), but I'm wondering how the optoisolator works. Does it have its own power rails, or can I just treat it like a passive component?
It's essentially passive. You drive the LED side just like you'd drive any other LED. The transistor side (the output) requires a pull-up to the supply voltage of your choice; you take the output at the collector.  You need enough LED drive to completely turn the transistor on so it pulls low enough to ensure that whatever it connects to recognizes a valid logic low. Also the pullup resistor value needs to be selected such that the turn-off time isn't excessively long. When the transistor turns off, the pullup makes the output a logic high, and the stiffer the pullup, the faster the rise time.

So there it is.

-a
 

Consul

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Andy Peters said:
I was able to find a SID data sheet, which helps ... and the Nexys2 board has a Spartan3E FPGA.

Thanks! I've been looking all over for that. I had found this version of it, which seems pretty complete except I can't find anything about voltage levels.

The short answer is:
a) Set the output-only (from the FPGA) pins to use an IOSTANDARD of LVCMOS33. The SID logic inputs need only 2V for a valid logic high, which is easily driven by LVCMOS33 outputs which swing to the 3.3V rail. No level translation needed.

I didn't know this about the SID. Sounds like a very well-designed chip.

b) For the bidirectional data bus, you're kind of stuck, because the series current limiting resistors required to keep the FPGA inputs from burning up make it difficult for the output to drive the SID inputs to the appropriate level. Do some math to check this. I wouldn't do it.

I don't think I need bidirectionality. That was mainly to allow a program to read the registers storing the A/D converter value, for game paddles and so on. So I might be okay here. The data bus becomes an input or output based upon which address is selected on the address bus, if I read the data sheet right.

I assume you'll have to build some sort of board onto which the SID and its related parts need to be installed, and you're afraid of SMD.

It's not so much that I'm afraid of SMD. I'm just not equipped for it, and don't have much money. I can either start building stuff, or continue to buy gear. I think I'd rather build stuff.

If you have the I/O available, then drive each SID from its own FPGA pins. The FPGA won't have any problem doing so. Of course you'll need four data buses.

I definitely have enough I/O available. If I don't need the level shifting, this will be much easier.

It's essentially passive. You drive the LED side just like you'd drive any other LED. The transistor side (the output) requires a pull-up to the supply voltage of your choice; you take the output at the collector.  You need enough LED drive to completely turn the transistor on so it pulls low enough to ensure that whatever it connects to recognizes a valid logic low. Also the pullup resistor value needs to be selected such that the turn-off time isn't excessively long. When the transistor turns off, the pullup makes the output a logic high, and the stiffer the pullup, the faster the rise time.

Thank you very much for all the help. This should be a pretty cool project if I can find all the matching SIDs that I need. :)
 

Consul

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Okay, I did learn in the data sheet that there is no envelope controlling the filter cutoff. For that, they set up a read-only register for ENV3 that could be read and then applied to the filter via software. That would be the only reason to need a bidirectional data bus. I think it would probably be possible to make an envelope generator on the FPGA that would work fine, though it might be a bit of work.

EDIT: It turns out there is code out there that implements envelopes for FPGAs (most of it's in Verilog - I learned VHDL, but I don't think that matters). Also, I could implement pitch envelopes in this same way.
 

Andy Peters

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dmlandrum said:
Andy Peters said:
The short answer is:
a) Set the output-only (from the FPGA) pins to use an IOSTANDARD of LVCMOS33. The SID logic inputs need only 2V for a valid logic high, which is easily driven by LVCMOS33 outputs which swing to the 3.3V rail. No level translation needed.

I didn't know this about the SID. Sounds like a very well-designed chip.

It was designed to the standards of the day. What I describe is nothing out of the ordinary.

I assume you'll have to build some sort of board onto which the SID and its related parts need to be installed, and you're afraid of SMD.

It's not so much that I'm afraid of SMD. I'm just not equipped for it, and don't have much money. I can either start building stuff, or continue to buy gear. I think I'd rather build stuff.

There's nothing you really need to buy to do SMD, except for maybe a soldering iron tip of appropriate size. You can buy simple boards that let you mount an SOIC and it's got pads to which you can solder 0805 or 1206 passives as well as wires to other boards.

Having said that -- the sooner you embrace SMD, the better, because DIP is going away. It's rare that new parts are available in DIP.

-a
 

Consul

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Andy Peters said:
It was designed to the standards of the day. What I describe is nothing out of the ordinary.

I thought the standard minimum for logical high was 4.1 to 4.2volts for 5-volt logic, but I guess that's neither here nor there at this point. Either way, it looks like I can make this whole project work without too much fuss. Thanks for the help!
 

PRR

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> I have a couple of SID chips

Do we get a clue? Or are we supposed to remember 1986??

Thanks, Andy.

> I thought the standard minimum for logical high was 4.1 to 4.2volts for 5-volt logic

Not at all.

No "standard".

RTL needed one base-emitter drop plus a bit more for the base resistor, plus a bit more for margin.

TTL needs a couple diode-drops, 1.2V, plus some margin. 1.5V works slow for one TTL under a new moon. We pull them up to 3V to be sure in fast complex noisy systems and full moons.

CMOS at 5V switches somewhere in the middle, usually 2V-3V, but the sheet shows a larger zone of uncertainty and you must go over 3.3V to cover a worst-case slop.

I don't think older TTL ever pulled-up above 3.8V. And at low temps, not even that far, or not fast into capacitive loads. When driving CMOS inputs we added pull-up resistors just to be sure of having some margin left on nights like this.

An awful lot of smarter chips adopt a 1.2V (or so) reference with low tempco. This tends to be slower or more transistors but as you see it is a worthy feature, and not costly on a fancy chip.
 

JohnRoberts

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You ned to look at the data sheets for different logic families to see the guaranteed logic hi/logic lo voltages. While for one off designs you might get lucky, for real production design you need to operate within the guaranteed margins, so always works.

Another issue when operating between different logic voltages is understanding the function and sensitivity of that logic line.  Low voltage families will sometimes accommodate and open drain configuration where say a 3.3V logic can interface with 5V logic using a pull up resistor, but be aware, this passive pull up can cause problems too. I had one application where I was driving a 5V clock input from a 3.3V logic output. The slow ramp through the 5V logic threshold, combined with noise on the pull up supply, resulted in erratic multiple false clocks.

As has been mentioned you can usually find a 5V logic family the works with 3.3V inputs, check the data sheets for the different variants of common logic gates.

JR
 

Consul

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Thanks, all!

After all is said and done, the first thing I'm going to get done is MIDI input and processing. I plan to make videos and write blog posts and all that documenting the project, so as I make progress, I'll probably mention it around here somewhere. If anyone's interested, of course.
 
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