Samuel Groner
Well-known member
Hi
Been a while since we've seen new elaborated discrete opamps; about time to present some recent work from my side.
First we have a successor to the SGA-SOA-1: SGA-SOA-2_r1.pdf
The changes are subtle, but worth a more detailed discussion. First we now have inclusive Miller compensation, i.e. the output stage is included in the local loop of the compensation capacitor C2. This frees the second stage (Q4) from providing the current to charge C2; benefit is much reduced distortion at high frequencies (100 kHz THD+N dropped ten times) and lower output impedance. The former is also a result from somwhat higher slew-rate. The input stage degeneration resistors R1/R2 are increased in value which in turn allows reduction of C2. R4 is introduced to balance the collector voltages of Q1 and Q2 which somewhat improves CMRR; same applies for the use of a transistor (Q3) with higher hFE for the tail current source and the use of a single inductor in the input stage. To reduce the short-circuit output current the output stage emitter resistors are increased (R10, R11); to get the quiescent current back to 15 mA R9 is added.
All the improvements have been achieved at unchanged parts count and quiescent current. The resulting typical specifications for 600 Ohm load and ±18 V supplies are as follows:
Input offset voltage: < 20 mV
Input bias current: -1.1 uA
Input voltage noise: 1.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 0.6 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 80 dB
Gain-bandwidth product: 40 MHz at 10 kHz
Unity-gain bandwidth: 15 MHz
Slew rate: ±14 V/us
Output swing: ±17 V
Class A output drive: 600 Ohm for full voltage swing
Maximum output current: ±230 mA
Supply current: 21 mA (no load)
R6 should be adjusted if different supply voltages are used. Suggested values are 18 kOhm (±15 V), 15 kOhm (±12 V) and 12 kOhm (±10 V).
Second an opamp with very low voltage noise: SGA-LNA-1_r1.pdf
A fully complementary topology is used; this effectively reduces voltage noise by 3 dB and cancels input bias currents. Resulting voltage noise is low enough for a MC preamp. The design is stable at noise gains of about 3, and no adaptations for lower supply rails are needed. The typical specifications for 600 Ohm load and ±24 V supplies are as follows:
Input offset voltage: < 10 mV
Input bias current: ±100 nA
Input voltage noise: 0.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 1.7 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 80 dB
Gain-bandwidth product: 145 MHz at 100 kHz
Slew rate: ±48 V/us
Output swing: ±22 V
Class A output drive: 1.4 kOhm for full voltage swing
Maximum output current: ±50 mA
Supply current: 25 mA (no load)
Third a general-purpose opamp designed to operate at high voltages up to ±40 V: SGA-HVA-1_r1.pdf
The design uses the generic two-stage topology which is well know from D. Self's work and the JE-990 opamp. There are a few unusal details though which might be interesting; first the base-current errors from the input stage collector load mirror (Q3 and Q4) are first-order cancelled by operating Q6 at twice the collector current of Q3/Q4; the voltage divider formed by R6 and R7 allows the use of transistor types with low breakdown voltage but high hFE for Q3-Q5. D3 is used to operate Q1 and Q2 at similar collector voltage (this is maintained over temperature) for improved CMRR. C1 provides a high-frequency feedforward path around Q5. This prevents gain peaking at some hundred MHz and keeps the inclusive Miller loop formed by C3 stable. R6 should be altered for lower supply voltages to maintain the 1.6 mA bias through D3/D4. Suggested values are 33k (±30 V), 27k (±24 V), 20k (±18 V), 16k (±15 V), 12k (±12 V) and 10k (±10 V).
I'm pretty pleased with the performance of this amplifier; the input offset measured at the prototype was just half a mV, indicating that second order effects from the current mirror and second stage are well addressed. Distortion is very low at least in inverting mode, rivaling that of the very best IC opamps. And the quiescent current is low for a discrete implementation. The typical specifications for 600 Ohm load and ±40 V supplies are as follows:
Input offset voltage: < 5 mV
Input bias current: -1.1 uA
Input voltage noise: 1.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 0.6 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 130 dB
Gain-bandwidth product: 65 MHz at 10 kHz
Unity-gain bandwidth: 10 MHz
Slew rate: ±21.7 V/us
Output swing: +37.3/-37.5 V
Class A output drive: 1.9 kOhm for full voltage swing
Maximum output current: +85/-95 mA
Supply current: 18 mA (no load)
I have little intention to design suitable 2520-style PCBs, but if someone want's to go ahead feel free to do so. At least the first two designs should not present serious problems as their parts count is relatively low.
Samuel
Been a while since we've seen new elaborated discrete opamps; about time to present some recent work from my side.
First we have a successor to the SGA-SOA-1: SGA-SOA-2_r1.pdf
The changes are subtle, but worth a more detailed discussion. First we now have inclusive Miller compensation, i.e. the output stage is included in the local loop of the compensation capacitor C2. This frees the second stage (Q4) from providing the current to charge C2; benefit is much reduced distortion at high frequencies (100 kHz THD+N dropped ten times) and lower output impedance. The former is also a result from somwhat higher slew-rate. The input stage degeneration resistors R1/R2 are increased in value which in turn allows reduction of C2. R4 is introduced to balance the collector voltages of Q1 and Q2 which somewhat improves CMRR; same applies for the use of a transistor (Q3) with higher hFE for the tail current source and the use of a single inductor in the input stage. To reduce the short-circuit output current the output stage emitter resistors are increased (R10, R11); to get the quiescent current back to 15 mA R9 is added.
All the improvements have been achieved at unchanged parts count and quiescent current. The resulting typical specifications for 600 Ohm load and ±18 V supplies are as follows:
Input offset voltage: < 20 mV
Input bias current: -1.1 uA
Input voltage noise: 1.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 0.6 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 80 dB
Gain-bandwidth product: 40 MHz at 10 kHz
Unity-gain bandwidth: 15 MHz
Slew rate: ±14 V/us
Output swing: ±17 V
Class A output drive: 600 Ohm for full voltage swing
Maximum output current: ±230 mA
Supply current: 21 mA (no load)
R6 should be adjusted if different supply voltages are used. Suggested values are 18 kOhm (±15 V), 15 kOhm (±12 V) and 12 kOhm (±10 V).
Second an opamp with very low voltage noise: SGA-LNA-1_r1.pdf
A fully complementary topology is used; this effectively reduces voltage noise by 3 dB and cancels input bias currents. Resulting voltage noise is low enough for a MC preamp. The design is stable at noise gains of about 3, and no adaptations for lower supply rails are needed. The typical specifications for 600 Ohm load and ±24 V supplies are as follows:
Input offset voltage: < 10 mV
Input bias current: ±100 nA
Input voltage noise: 0.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 1.7 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 80 dB
Gain-bandwidth product: 145 MHz at 100 kHz
Slew rate: ±48 V/us
Output swing: ±22 V
Class A output drive: 1.4 kOhm for full voltage swing
Maximum output current: ±50 mA
Supply current: 25 mA (no load)
Third a general-purpose opamp designed to operate at high voltages up to ±40 V: SGA-HVA-1_r1.pdf
The design uses the generic two-stage topology which is well know from D. Self's work and the JE-990 opamp. There are a few unusal details though which might be interesting; first the base-current errors from the input stage collector load mirror (Q3 and Q4) are first-order cancelled by operating Q6 at twice the collector current of Q3/Q4; the voltage divider formed by R6 and R7 allows the use of transistor types with low breakdown voltage but high hFE for Q3-Q5. D3 is used to operate Q1 and Q2 at similar collector voltage (this is maintained over temperature) for improved CMRR. C1 provides a high-frequency feedforward path around Q5. This prevents gain peaking at some hundred MHz and keeps the inclusive Miller loop formed by C3 stable. R6 should be altered for lower supply voltages to maintain the 1.6 mA bias through D3/D4. Suggested values are 33k (±30 V), 27k (±24 V), 20k (±18 V), 16k (±15 V), 12k (±12 V) and 10k (±10 V).
I'm pretty pleased with the performance of this amplifier; the input offset measured at the prototype was just half a mV, indicating that second order effects from the current mirror and second stage are well addressed. Distortion is very low at least in inverting mode, rivaling that of the very best IC opamps. And the quiescent current is low for a discrete implementation. The typical specifications for 600 Ohm load and ±40 V supplies are as follows:
Input offset voltage: < 5 mV
Input bias current: -1.1 uA
Input voltage noise: 1.5 nV/sqrt(Hz) at 1 kHz
Current noise density: 0.6 pA/sqrt(Hz) at 1 kHz
Open loop voltage gain: 130 dB
Gain-bandwidth product: 65 MHz at 10 kHz
Unity-gain bandwidth: 10 MHz
Slew rate: ±21.7 V/us
Output swing: +37.3/-37.5 V
Class A output drive: 1.9 kOhm for full voltage swing
Maximum output current: +85/-95 mA
Supply current: 18 mA (no load)
I have little intention to design suitable 2520-style PCBs, but if someone want's to go ahead feel free to do so. At least the first two designs should not present serious problems as their parts count is relatively low.
Samuel